MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 123
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 123 of 481
- Download datasheet (2Mb)
For details on the DRAM refresh controller, see 3.10 Dynamic Ram Refresh Controller.
4.2 SDMA CHANNELS
Six serial (SDMA) channels are associated with the three full-duplex SCCs. Each channel
is permanently assigned to service the receive or transmit operation of one of the SCCs and
is always available, regardless of the SCC protocol chosen.
The SDMA channels allow flexibility in managing the data flow. The user can, on a buffer-
by-buffer basis, determine whether data should be transferred between the SCCs and ex-
ternal memory or between the SCCs and on-chip dual-port RAM. This choice is controlled
in each SCC buffer descriptor. The SCC to external memory path bypasses the dual-port
RAM by allowing the SDMA channel to arbitrate for the M68000 bus directly. The SCC to
dual-port RAM path saves external memory and eliminates the need to arbitrate for the bus.
Figure 4-2 shows the paths of the data flow. Data from the SCCs may be routed directly to
external RAM as shown in path 1. In path 2, data is sent over the peripheral bus to the in-
ternal dual-port RAM. The SMCs and SCP, shown in path 3, always route their data to the
dual-port RAM since they only receive and transmit a byte at a time.
MOTOROLA
3. DRAM Refresh Controller
4. Commands Issued to the Command Register
5. SCC1 Receive Channel
6. SCC1 Transmit Channel
7. SCC2 Receive Channel
8. SCC2 Transmit Channel
9. SCC3 Receive Channel
10. SCC3 Transmit Channel
11. SMC1 Receive Channel
12. SMC1 Transmit Channel
13. SMC2 Receive Channel
14. SMC2 Transmit Channel
15. SCP Receive Channel
16. SCP Transmit Channel
MC68302 USER’S MANUAL
Communications Processor (CP)
4-3
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