MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 395

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
porarily halt any IDMA accesses. The SDMAs only use the M68000 bus for a single bus cy-
cle before giving up the bus, so priority between SDMAs is not an issue. In this system, if an
SDMA channel from the slave requests service at the same time as an SDMA channel from
the master, the slave SDMA will go first.
With multiple slaves (i.e., multiple external bus masters from the standpoint of the master
MC68302), external logic must prioritize the various BR signals. The BGACK and BCLR sig-
nals can be connected as shown in Figure D-20, but the BR and BG signals must be routed
to the external bus arbiter.
D.7.6 Final Notes
It is important for the slave to negate its BR pin quickly after it asserts BGACK to meet the
master's bus arbitration timing specifications. Thus, a 820 pullup resistor is used in Figure
D-20.
Will the slave SDMA channels move SCC data to/from the low half of memory or the high
half of memory? If the decision is the low half of memory, the following notes about A23
should be considered.
Since A23 on the master and the slave are not driven by the address bus, they must be at
the proper level before beginning accesses to and from the slave MC68302. Thus, the
slave's A23 pullup may have to be reduced from 10k to 1k to give a fast enough rise time
(for instance, a slave SDMA access is immediately followed by a master access to the
slave).
The decision of whether to pull the master's A23 pin up or down is made based on whether
the SDMA on the slave will be storing its SCC data into the high half or the low half of mem-
ory, respectively. A 1k resistor may be required in this case as well. However, if the master
MC68302 chip-select logic is used by the slave, the chip-select comparison for the A23 pin
can be disabled. (If this trick is used, it is important that no peripherals or memory be
mapped to the chip select's corresponding area in the upper half of system memory).
D.8 USING THE MC68302 TRANSPARENT MODE
The following paragraphs describe different ways that the totally transparent (promiscuous)
mode on the MC68302 serial channels can be used.
D.8.1 Transparent Mode Definition
Transparent mode allows the transmission and reception of serial data over a serial com-
munications controller (SCC) without any modification to that data stream. Contrast this with
HDLC mode, where zero bits are occasionally inserted during transmission and stripped
during reception, and with UART mode, where start and stop bits are inserted and stripped.
Transparent mode provides a clear channel on which no bit-level manipulation is performed
by the SCC. Any protocol run on transparent mode is performed in software. The job of an
SCC in transparent mode is to function simply as a high-speed serial-parallel converter.
Transparent mode on the MC68302 also means a synchronous protocol; thus, a clock edge
must be provided with each bit of data received or transmitted. Contrast this with the UART
MOTOROLA
MC68302 USER’S MANUAL
D-45