MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 194

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
the SCC mode register when that SCC is configured for HDLC. The read-write HDLC mode
register is cleared by reset.
NOF3–NOF0—Minimum Number of Flags between Frames or before Frames (0 to 15
Flags)
C32—CRC16/CRC32
FSE—Flag Sharing Enable
Bit 9—Reserved for future use.
RTE—Retransmit Enable
FLG—Transmit Flags/Idles between Frames and Control the RTS Pin
4-74
NOF3
15
If NOF3–NOF0 = 0000, then no flags will be inserted between frames. Thus, the closing
flag of one frame will be followed immediately by the opening flag of the next frame in the
case of back-to-back frames.
Automatic retransmission occurs if a CTS lost condition happens on the first or second
buffer of the frame. See 4.5.12.8 HDLC Error-Handling Procedure.
0 = 16-bit CCITT CRC (X 16 + X 12 + X 5 + 1 )
1 = 32-bit CCITT CRC (X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7
0 = Normal operation
1 = If NOF3–NOF0 = 0000, then a single shared flag is transmitted between back- to-
0 = No automatic retransmission will be performed.
1 = Automatic retransmit enabled
0 = Send ones between frames; RTS is negated between frames. If NOF–NOF0 is
1 = Send flags between frames. RTS is always asserted. The CP polls the Tx BD ready
NOF2 NOF1
14
+ X 5 + X 4 + X 2 + X 1 + 1)
back frames. Other values of NOF3–NOF0 are decremented by one when FSE is
set. This is useful in Signaling System #7 applications.
greater than zero, RTS will be negated for a multiple of eight transmit clocks. The
HDLC controller can transmit ones in both the NRZ and NRZI data encoding for-
mats. The CP polls the Tx BD ready bit every 16 transmit clocks.
bit every eight transmit clocks.
13
This bit may be dynamically modified. If toggled from a one to a
zero between frames, a maximum of two additional flags will be
transmitted before the idle condition will begin. Toggling FLG will
never result in partial flags being transmitted.
NOF0
12
C32
11
FSE
10
MC68302 USER’S MANUAL
—
9
RTE
NOTE
8
FLG
7
ENC
6
5
COMMON SCC MODE BITS
MOTOROLA
0