MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 223
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
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Communications Processor (CP)
begins. However, if a character is not SOH, ENQ, DLE, or SYNC, hunt mode is again en-
tered. On asynchronous links, byte synchronization is achieved by the start/stop protocol of
the UART. The DDCMP controller is now byte-synchronized and performs SYN1–SYN2
stripping, until receiving one of the three user-defined special starting bytes (SOH for data
messages, ENQ for control messages, and DLE for maintenance messages).
If a match is detected, the DDCMP controller fetches the next BD and, if it is empty, starts
to transfer the incoming header to the BD's associated data buffer. The DDCMP controller
counts the bytes of the fixed-length header and compares the received header address field
to the four user-defined values after masking the result with the address mask. When a
match is detected, the DDCMP controller continues to transfer the incoming message to the
data buffer. The header CRC field (CRC1) is checked and is written to the data buffer. The
DDCMP controller updates the CRC error (CR) bit, sets the header (H) bit, writes the mes-
sage type and status bits into the BD, and clears the empty bit. It next generates a maskable
receive block interrupt (RBK), indicating that a header has been received and is in memory.
If the header was a control message, the DDCMP controller waits for a new message.
If there is no match in address comparison and the header is error free, the DDCMP con-
troller will use the same buffer for the next message. To maintain synchronization, the DDC-
MP controller counts the data length based on the count field contained in the header.
When the data buffer has been filled, the DDCMP controller clears the empty bit in the BD
and generates a maskable received buffer interrupt (RBD). If the incoming message ex-
ceeds the length of the data buffer, the DDCMP controller fetches the next BD in the table,
and, if it is empty, continues to transfer the rest of the message to the new data buffer. When
the message ends, the CRC2 field is checked and written to the data buffer. The DDCMP
controller sets the last bit, writes the message type and other status bits into the BD, and
clears the empty bit. Following this, it generates an RBK, indicating that a message has
been received and is in memory. The DDCMP controller then waits for a new message.
4.5.14.3 DDCMP Memory Map
When configured to operate in DDCMP mode, the IMP overlays the structure illustrated in
Table 4-9 onto the protocol-specific area of that SCC's parameter RAM. Refer to 2.8
MC68302 Memory Map for the placement of the three SCC parameter RAM areas and to
Table 4-5 for the other parameter RAM values.
MOTOROLA
MC68302 USER’S MANUAL
4-103
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