MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 262
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
Communications Processor (CP)
4.7.4.2 SMC1 Transmit Buffer Descriptor
The CP reports information about this transmit byte through the BD.
R—Ready
In GCI mode, when the IMP implements the monitor channel protocol, it will clear this bit af-
ter receiving an acknowledgment on the A bit. When the SMC1 data should be transmitted
and this bit is cleared, the channel will retransmit the previous data until new data is provided
by the M68000 core.
L—Last (EOM)
AR—Abort Request
Bits 12–10—Reserved for future use.
AB—Transmit A Bit Value
EB—Transmit E Bit Value
Data—Data Field
4.7.4.3 SMC2 Receive Buffer Descriptor
In the IDL mode, this BD is identical to the SMC1 receive BD. In the GCI mode, SMC2 is
used to control the C/I channel.
4-142
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol.
When this bit is set, the SMC1 channel will transmit the buffer's data and then the end of
message (EOM) indication on the E bit.
This bit is valid only in GCI mode when the IMP implements the monitor channel protocol.
This bit is set by the IMP when an abort request was received on the A bit. The SMC1
transmitter will transmit EOM on the E bit.
This bit is valid only in GCI mode when the monitor channel is in transparent mode.
This bit is valid only in GCI mode when the monitor channel is in transparent mode.
The data field contains the data to be transmitted by SMC1.
15
15
E
R
0 = This bit is cleared by the CP after transmission. The Tx BD is now available to the
1 = This bit is set by the M68000 core to indicate that the data byte associated with this
14
M68000 core.
BD is ready for transmission.
14
L
13
AR
12
RESERVED
—
MC68302 USER’S MANUAL
10
AB
9
EB
8
6
7
5
C/I
DATA
2
MOTOROLA
0
1
0
0
0
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