MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 27
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 27 of 481
- Download datasheet (2Mb)
The use of a unique arbitration scheme and synchronous transfers between the micropro-
cessor and dual-port RAM gives zero wait-state operation to the M68000 microprocessor
core. The dual-port RAM can be accessed by the CP main controller (RISC) once every
clock cycle for either read or write operations. When the M68000 core accesses the dual-
port RAM, each access is pipelined along with the CP accesses so that data is read or writ-
ten without conflict. The net effect is the loss of a single memory access by the CP main
controller per M68000 core access.
The buffer memory structure of the MC68302 can be configured to closely match I/O chan-
nel requirements by careful selection of buffer size and buffer linking. The interrupt structure
is also programmable so that the on-chip M68000 processor can be off-loaded from the pe-
ripheral bit-handling functions to perform higher layer application software or protocol pro-
cessing.
1.4 NMSI COMMUNICATIONS-ORIENTED ENVIRONMENT
When the interface to equipment or proprietary networks requires the use of standard con-
trol and data signals, the MC68302 can be programmed into the nonmultiplexed serial inter-
face (NMSI) mode. This mode, which is available for one, two, or all three SCC ports, can
be selected while the other ports use one of the multiplexed interface modes (IDL, GCI, or
PCM highway).
MOTOROLA
COMMUNICATIONS
MICROCODED
CONTROLLER
M68000
(RISC)
CORE
Figure 1-3. MC68302 System Design
CONTROLLER
INTERRUPT
MC68302 USER’S MANUAL
CHANNELS
CHANNELS
3 SERIAL
6 DMA
PERIPHERAL BUS
1 GENERAL-
PURPOSE
CHANNEL
DMA
SYSTEM BUS
1152 BYTES
DUAL-PORT
CHANNELS
OTHER
SERIAL
68000
RAM
ADDITIONAL
FEATURES
3 TIMERS
AND
MC68302 IMP
General Description
PERIPHERALS
RAM / ROM
OTHER
1-5
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