MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 166

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
The UART may receive fractional stop bits. The next character's start bit may begin anytime
after the 11th internal clock of the previous character's first stop bit (the UART uses a 16X
clock).
The UART transmit shift register transmits the outgoing data on the TXD pin as shown in
Figure 4-17. Data is clocked synchronously with the transmit clock, which may have either
an internal or external source. The order of bit transmission is as stated for reception.
Only the data portion of the UART frame is actually stored in the data buffers. The start and
stop bits are always generated and stripped by the UART controller. The parity bit may also
be generated in the case of transmission, and checked during reception. Although parity is
not stored in the data buffer, its value may be inferred by the reporting mechanism in the
data buffer (i.e., characters with parity errors are identified). Similarly, the optional address
bit is not stored in the transmit or receive data buffer, but is implied from the buffer descriptor
itself. Parity is generated and checked for the address bit, when present.
4.5.11.2 Asynchronous DDCMP MODE
The IMP also allows the DDCMP protocol to be run over an asynchronous connection, using
the UART. The description of this operation is contained in 4.5.14 DDCMP Controller. This
operation uses the DDCMP buffer structures and the DDCMP-specific parameter RAM;
however, the SCC mode register must be configured as a UART. The proper programming
of the UART mode register to obtain asynchronous DDCMP is covered in 4.5.11.13 UART
Mode Register.
4.5.11.3 UART Memory Map
When configured to operate in UART mode, the IMP overlays the structure (see Table 4-6)
onto the protocol-specific area of that SCC's parameter RAM. Refer to 2.8 MC68302 Mem-
ory Map for the placement of the three SCC parameter RAM areas and to Table 4-5 for the
other parameter RAM values.
4-46
# Initialized by the user (M68000 core).
SCC Base + 9C #
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2 #
SCC Base + A4 #
SCC Base + A6 #
SCC Base + A8 #
SCC Base + AA #
SCC Base + AC #
SCC Base + AE
SCC Base + B0 #
SCC Base + B2 #
SCC Base + B4 #
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
Address
Table 4-7. UART Specific Parameter RAM
CHARACTER1
CHARACTER2
CHARACTER3
CHARACTER4
CHARACTER5
CHARACTER6
CHARACTER7
CHARACTER8
MAX_IDL
UADDR1
UADDR2
BRKCR
FRMEC
NOSEC
PAREC
BRKEC
RCCR
Name
IDLC
MC68302 USER’S MANUAL
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Maximum IDLE Characters (Receive)
Temporary Receive IDLE Counter
Break Count Register (Transmit)
Receive Parity Error Counter
Receive Framing Error Counter
Receive Noise Counter
Receive Break Condition Counter
UART ADDRESS Character 1
UART ADDRESS Character 2
Receive Control Character Register
CONTROL Character 1
CONTROL Character 2
CONTROL Character 3
CONTROL Character 4
CONTROL Character 5
CONTROL Character 6
CONTROL Character 7
CONTROL Character 8
Description
MOTOROLA