MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 374

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
er register (SAPR). The pointer to the destination is located in the destination address point-
er register (DAPR). The byte count register (BCR) specifies the number of bytes to be
transferred and is decremented once for each byte transferred. Note that the six SDMA
channels on the MC68302 have a higher priority than the IDMA (unless the IDMA is perform-
ing a maximum rate burst).
D.5.2 IDMA Software Initialization
Information that describes the data block to be moved, the transfer methods, and the control
options is loaded into the channel mode register (CMR). See Table D-2 for these required
selections. Loading the SAPR, DAPR, and BCR are also part of the initialization procedure.
If the functions of the DREQ, DACK, and DONE pins are required, then their corresponding
bits must be enabled in the port A control register (PACNT).
D.5.3 IDMA Bus Arbitration Signals
Whenever the IDMA wants to transfer data, it must arbitrate for the external bus. Two inter-
nal signals are used: IDMA bus request (IDBR) and IDMA bus grant (IDBG). When no ex-
ternal resource controls the bus (BGACK is negated) nor any internal resource (such as the
SCCs) requires the use of the bus, then the IDMA can be granted the bus when it asserts
(internally) IDBR. Obtaining bus mastership occurs when 1) AS and BGACK are high (ne-
gated) and 2) external BR and BG are not indicating an external master wants the bus. To
indicate that the IDMA has taken control of the bus, BGACK is asserted while BR and BG
are not asserted. The IDMA function code bits in the function code register (FCR) can be
further used to distinguish between the source and destination accesses.
D.5.4 Triggering External IDMA Transfers
The data request (DREQ) input signal should be asserted by a peripheral when it requires
service. The MC68302 responds with data acknowledge (DACK) output signal which as-
serts when the IDMA is moving data from/to the peripheral device. A third signal, DONE, in-
dicates when the last DMA transfer cycle is in progress. The bidirectional DONE signal is
asserted by the IDMA when the BCR has decremented to zero or can be asserted by the
peripheral to terminate the data transfer.
D.5.5 Performing Internally Generated IDMA Transfers
The procedure to move blocks of data from one memory space to another can be achieved
by first loading the SAPR, DAPR, BCR, and CMR. The DMA transfer sequence begins by
setting the STR bit (see Table D-2) in the CMR. The transfer stops when the BCR has dec-
remented to zero, the external DONE pin is asserted externally, or the software clears the
STR bit in the CMR. The percentage of bus usage can be controlled by the BT bits to keep
the IDMA from exceeding 12.5, 25, 50, or 75 percent of the available bus bandwidth. The
transfer can also be interrupted by the BCLR signal, which can be activated through the
SDMA channels, or by an interrupt (see 3.8.3 System Control Bits).
D-24
MC68302 USER’S MANUAL
MOTOROLA