MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 276

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Signal Description
5.10 MC68302 BUS INTERFACE SIGNAL SUMMARY
Table 5-2 and Table 5-3 summarize all bus signals discussed in the previous paragraphs.
They show the direction of each pin for the following bus masters: M68000 core, IDMA,
SDMA (includes DRAM refresh), and external. Each bus master can access either internal
dual-port RAM and registers or an external device or memory. When an external bus master
accesses the internal dual-port RAM or registers, the access may be synchronous or asyn-
chronous.
When the M68000 core is disabled, BR and BG change their direction, and BCLR becomes
bidirectional.
5-12
**
***
A23–A1, FC2–FC0,
AS, UDS, LDS, R/W, RMC
BCLR
IAC
D15–D0 Read
D15–D0 Write
DTACK
BR
BG
BGACK
HALT
RESET
BERR
IPL2–IPL0
AVEC
IOUT2–IOUT0
If DTACK is generated automatically (internally) by the chip-select logic, then it is an output. Otherwise, it is an input.
tomatic vectoring only. AVEC instead of DTACK should be asserted during autovectoring
and should be high otherwise.
When the M68000 core is disabled, this pin operates as IOUT0. IOUT2–IOUT0 provide
the interrupt request output signals from the IMP interrupt controller to an external CPU
when the M68000 core is disabled.
chip-select logic detects address conflict or write protect violation. BERR may be asserted by external logic in all
cases.
BERR is an open-drain output, and may be asserted by the IMP when the hardware watchdog is used or when the
Signal Name
Table 5-2. Bus Signal Summary—Core and External Master
I/O Open Drain
I/O Open Drain
I/O Open Drain
I/O Open Drain
I/O Open Drain
Pin Type
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
MC68302 USER’S MANUAL
Memory
Internal
Space
I/O
M68000 Core Master
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
***
Access To
External
Memory
Space
I/O
I/O
I/O
O
O
O
O
**
O
O
I
I
I
I
I
***
Memory
Internal
Space
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
***
External Master
Access To
MOTOROLA
External
Memory
Space
I/O
O
O
**
O
O
I
I
I
I
I
I
I
I
I
***