MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 412

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
The L1SY1-L1SY0 signals determine 1) when clocks are sent to the particular SCC and 2)
when the synchronization signal is sent to the SCC. If the L1SY1-L1SY0 signals are not ac-
tive, then the SCC is not being clocked. The rising edge of L1SY1-L1SY0 starts the clocking
and sends an internal synchronization pulse to the SCC. These facts are very important in
determining when the first byte of real data from a buffer will be transmitted onto the PCM.
In transparent mode, if data is not ready to transmit, $FFs will be sent during the time slot.
Once data transfer begins, data will be clocked out during every clock of the time slot. When
the time slot ends, the SCC will wait without being clocked until the next time slot arrives.
Similarly, on the receive side, data and the clock will only be presented to the SCC when
that SCC's time slot is active.
When using transparent mode with PCM, it is often of interest to know exactly when the very
first buffer of transmit data will go out. The RTS signal gives an important clue here. Once
the RTS signal for an SCC is asserted, the next rising edge of the L1SY1-L1SY0 pins for
this channel (i.e., the SCC's next time slot) will begin clocking out the following pattern:
where data1 is the first byte of data stored in the transmit data buffer. For example, if the
PCM was configured with individual 8-bit time slots for this SCC, $FF would be clocked on
the first time slot, data1 on the second, etc. It is assumed in that this buffer in this exam-
ple does not immediately follow the previous buffer. A string of buffers with their L bits
cleared will follow each other immediately without any delay—only the first will have this de-
lay.
From the time the ENT bit is set and a buffer is ready to transmit, it can take a number of
serial clocks (usually less than 36) for RTS to be asserted (it could be more for higher data
rates). Thus, this clock delay must be taken into account if data transmission delays need
to be consistent. The delay can be accounted for by synchronizing the setting of the ENT bit
with the time slot itself. If the time slot is long, it should be sufficient to set the ENT bit before
one time slot to guarantee data transmission during the next time slot (see Figure D-30). The
algorithm can work as follows:
D-62
$FF, data1, data2, data3, . . .
1. After the last buffer is transmitted, give STOP TRANSMIT command.
2. Clear ENT.
3. Give RESTART TRANSMIT command.
4. Set ready bit of next Tx BD to transmit.
5. Generate interrupt to MC68302 on falling L1SY1 /L1SY0 pin.
6. Now that time slot is inactive, set ENT bit.
MC68302 USER’S MANUAL
MOTOROLA