MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 37
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
Other bus masters besides the M68000 may also output function codes during their bus cy-
cles. On the MC68302, this capability is provided for each potential internal bus master (i.e.,
the IDMA, SDMA, and DRAM refresh units). Also on the MC68302, provision is made for the
decoding of function codes that are output from external bus masters (e.g., in the chip-select
generation logic).
In computer design, function code information can be used to protect certain portions of the
address map from unauthorized access or even to extend the addressable range beyond
the M68000 16-Mbyte address limit. However, in controller applications, function codes are
used most often as a debugging aid. Furthermore, in many controller applications, the
M68000 stays continuously in the supervisor state.
All exception processing occurs in the supervisor state, regardless of the state of the S bit
when the exception occurs. The bus cycles generated during exception processing are clas-
sified as supervisor references. All stacking operations during exception processing use the
SSP.
The user state is the lower state of privilege. For instruction execution, the user state is de-
termined by the S bit of the SR; if the S bit is negated (low), the processor is executing in-
structions in the user state. Most instructions execute identically in either user state or
supervisor state. However, instructions having important system effects are privileged. User
programs are not permitted to execute the STOP instruction or the RESET instruction. To
ensure that a user program cannot enter the supervisor state except in a controlled manner,
the instructions which modify the entire SR are privileged. To aid in debugging programs to
be used in operating systems, the move-to-user-stack-pointer (MOVE to USP) and move-
from-user-stack-pointer (MOVE from USP) instructions are also privileged.
The supervisor state is the highest state of privilege. For instruction execution, the supervi-
sor state is determined by the S bit of the SR; if the S bit is asserted (high), the processor is
in the supervisor state. The bus cycles generated by instructions executed in the supervisor
state are classified as supervisor references. While the processor is in the supervisor privi-
lege state, those instructions using either the system stack pointer implicitly or address reg-
ister seven explicitly access the SSP.
MOTOROLA
* This is the function code output for the M68000 interrupt
acknowledge cycle.
FC2
Function Code Output
1
0
0
0
1
1
1
1
Table 2-4. M68000 Address Spaces
FC1
0
0
1
1
0
0
1
1
MC68302 USER’S MANUAL
FC0
0
1
0
1
0
1
0
1
Supervisor Program
Reference Class
Supervisor Data
User Program
(Unassigned)
(Unassigned)
(Unassigned)
CPU Space
User Data
*
MC68000/MC68008 Core
2-7
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