MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 63

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

External Device Termination
Error Termination
3.1.5 IDMA Programming
Once the channel has been initialized with all parameters required for a transfer operation,
it is started by setting the start operation (STR) bit in the CMR. After the channel has been
started, any register that describes the current operation may be read but not modified
(SAPR/DAPR, FCR, or BCR).
Once STR has been set, the channel is active and either accepts operand transfer requests
in external mode or generates requests automatically in internal mode. When the first valid
external request is recognized, the IDMA arbitrates for the bus. The DREQ input is ignored
until STR is set.
STR is cleared automatically when the BCR reaches zero and the channel transfer is either
terminated by DONE or the IDMA cycle is terminated by a bus error.
Channel transfer operation may be suspended at any time by clearing STR. In response,
any operand transfer in progress will be completed, and the bus will be released. No further
bus cycles will be started while STR remains negated. During this time, the M68000 core
may access IDMA internal registers to determine channel status or to alter operation. When
STR is set again, if a transfer request is pending, the IDMA will arbitrate for the bus and con-
tinue normal operation.
Interrupt handling for the IDMA is configured globally through the interrupt pending register
(IPR), the IMR, and the interrupt in-service register (ISR). Within the CMR in the IDMA, two
bits are used to either mask or enable the presence of an interrupt reported in the CSR of
the IDMA. One bit is used for masking normal termination; the other bit is used for masking
error termination. When these interrupt mask bits in the CMR (INTN and INTE) are cleared
and the IDMA status changes, status bits are set in the CSR but not in the IPR. When either
INTN or INTE is set and the corresponding event occurs, the appropriate bit is set in the IPR,
and, if this bit is not masked, the interrupt controller will interrupt the M68000 core.
MOTOROLA
If desired, a transfer may be terminated by the device even before the BCR is decrement-
ed to zero. If DONE is asserted one setup time prior to the S5 falling edge (i.e., before or
with DTACK) during a device access, then the channel operation will be terminated fol-
lowing the operand transfer (see the DNS bit in the CSR). STR is cleared, and an interrupt
is generated if INTN is set. The BCR is also decremented, and the SAPR and/or DAPR
are incremented in the normal fashion. The use of DONE is not limited to external request
generation only; it may also be used to externally terminate an internally generated IDMA
transfer sequence.
When a fatal error occurs during an IDMA bus cycle, a bus error is used to abort the cycle
and terminate the channel operation. STR is cleared, either BED or BES is set, and an
error interrupt is generated if INTE is set.
MC68302 USER’S MANUAL
System Integration Block (SIB)
3-13