MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 243

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

the protocol encoding itself. For instance, in a multiplexer, data from a high-speed time-mul-
tiplexed serial stream is multiplexed into multiple low-speed data streams. The concept is to
switch the data path but not alter the protocol encoded on that data path.
By appropriately setting the SCC mode register, any of the SCC channels can be configured
to function as a transparent controller. Transparent mode is achieved by setting the SCM
MODE1–MODE0 bits to 11 and setting the NTSYN bit (bit 13) to 1. Note that, if the NTSYN
bit is cleared, normal BISYNC operation will occur rather than transparent operation. See
4.5.13 BISYNC Controller for a description of BISYNC operation.
The SCC in transparent mode can work with IDL, GCI (IOM-2), PCM highway, or NMSI in-
terfaces. When the SCC in transparent mode is used with a modem interface (NMSI), the
SCC outputs are connected directly to the external pins. The modem interface uses seven
dedicated pins: transmit data (TXD), receive data (RXD), receive clock (RCLK), transmit
clock (TCLK), carrier detect or carrier detect sync (CD), clear to send (CTS), and request to
send (RTS).
The transparent controller consists of separate transmit and receive sections whose opera-
tions are asynchronous with the M68000 core and may be either synchronous or asynchro-
nous with respect to the other SCCs. Transparent mode on the MC68302 is a synchronous
protocol; thus, a clock edge must be provided with each bit of data received or transmitted.
Each clock can be supplied from either the internal baud rate generator or from external
pins. More information on the baud rate generator is available in 4.5.2 SCC Configuration
Register (SCON).
The main transparent controller features are as follows:
4.5.16.1 Transparent Channel Buffer Transmission Processing
When the M68000 core enables the transparent transmitter, it will start transmitting ones.
The transparent controller then polls the first BD in the transmit channel's BD table approx-
imately every 16 transmit clocks. When there is a buffer to transmit, the transparent control-
ler will fetch the data from memory and start transmitting the buffer. Transmission will not
begin until the internal transmit FIFO is preloaded and the SCC achieves synchronization.
See 4.5.16.5 Transparent Synchronization for details of the synchronization process.
When a BD's data is completely transmitted, the last bit (L) is checked in the BD. If the L bit
is cleared, then the transmitter moves immediately to the next buffer to begin its transmis-
sion, with no gap on the serial line between buffers. Failure to provide the next buffer in time
results in a transmit underrun, causing the TXE bit in the transparent event register to be set.
MOTOROLA
• Flexible Data Buffers
• External Sync Pin or BISYNC-Like Frame Sync on Receive
• Reverse Data Mode
• Interrupts on Buffers Transmitted or Received
• Clear to Send and Carrier Detect Lost Reporting
• Maskable Interrupt Available on Each Character Received
• Three Commands
MC68302 USER’S MANUAL
Communications Processor (CP)
4-123