MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 55
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 55 of 481
- Download datasheet (2Mb)
REQG—Request Generation
SAPI—Source Address Pointer (SAP) Increment
DAPI—Destination Address Pointer (DAP) Increment
SSIZE—Source Size
DSIZE—Destination Size
BT—Burst Transfer
MOTOROLA
The following decode shows the definitions for the REQG bits:
The following decode shows the definitions for the SSIZE bits.
The following decode shows the definitions for the DSIZE bits.
The BT bits control the maximum percentage of the M68000 bus that the IDMA can use
during each 1024 clock cycle period following the enabling of the IDMA. The IDMA runs
for a consecutive number of cycles up to its burst transfer percentage if bus clear (BCLR)
is not asserted and the BCR is greater than zero. The following decode shows these per-
centages.
00 = Internal request at limited rate (limited burst bandwidth) set by burst transfer (BT)
01 = Internal request at maximum rate (one burst)
10 = External request burst transfer mode (DREQ level sensitive)
11 = External request cycle steal (DREQ edge sensitive)
0 = SAP is not incremented after each transfer.
1 = SAP is incremented by one or two after each transfer, according to the source size
0 = DAP is not incremented after each transfer.
1 = DAP is incremented by one or two after each transfer, according to the destination
00 = Reserved
01 = Byte
10 = Word
11 = Reserved
00 = Reserved
01 = Byte
10 = Word
11 = Reserved
00 = IDMA gets up to 75% of the bus bandwidth.
01 = IDMA gets up to 50% of the bus bandwidth.
10 = IDMA gets up to 25% of the bus bandwidth.
11 = IDMA gets up to 12.5% of the bus bandwidth.
(SSIZE) bits and the starting address.
size (DSIZE) bits and the starting address.
bits
An interrupt will only be generated if the IDMA bit is set in the
IMR.
MC68302 USER’S MANUAL
NOTE
System Integration Block (SIB)
3-5
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