MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 117
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
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to the DRAM bank. The PAL generates the RAS and CAS lines for the DRAM chips and con-
trols the address multiplexing in the external address buffers. One of the MC68000 chip-se-
lect lines can be used as the DRAM bank enable signal, if desired.
The refresh operation is a byte read operation. Thus, UDS or LDS will be asserted from the
MC68302, but not both. A refresh to an odd address will assert LDS; whereas, a refresh to
an even address will assert UDS.
3.10.2 DRAM Refresh Controller Bus Timing
The DRAM refresh controller bus cycles are actually SDMA byte read accesses (see 4.2
SDMA Channels for more details). All timings, signals, and arbitration characteristics of
SDMA accesses apply to the DRAM refresh controller accesses. For example, DRAM re-
fresh cycles activate the BCLR signal, just like the SDMA. Note that the function code bits
may be used to distinguish DRAM refresh cycles from SDMA cycles, if desired.
A bus error on a DRAM refresh controller access causes the BERR channel number at offset
BASE + $67C to be written with a $0001. This is also the value written if the SCC1 receive
SDMA channel experiences a bus error; thus, these two sources cannot be distinguished
upon a bus error. The DRAM refresh SDMA channel and SCC1 receive SDMA channel are
separate and independent in all other respects.
3.10.3 Refresh Request Calculations
A typical 1-Mbyte DRAM needs one refresh cycle every 15.625 s. The DRAM refresh con-
troller is configured to execute one refresh cycle per request; thus, the PB8 pin should see
a high-to-low transition every 15.625 s. This is once every 260 cycles for a 16.67-MHz
clock. Note that one refresh per request minimizes the speed loss on the SCC channels.
MOTOROLA
TOUT OR BRG
PB8
MC68302
Figure 3-13. DRAM Control Block Diagram
DATA
MC68302 USER’S MANUAL
CONTROL
ADDRESS
BUFFERS
ADDRESS
MUX
System Integration Block (SIB)
DRAM
BANK
PAL
CONTROL
3-67
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