MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 211

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Error Counter
4.5.13.9 BISYNC Mode Register
Each SCC mode register is a 16-bit, memory-mapped, read-write register that controls the
SCC operation. The term BISYNC mode register refers to the protocol-specific bits (15–6)
of the SCC mode register when that SCC is configured for BISYNC. The read-write BISYNC
mode register is cleared by reset.
PM—Parity Mode
EXSYN—External Sync Mode
MOTOROLA
4. CRC Error. The channel updates the CRC error (CR) bit in the BD every time a char-
The CP main controller maintains one 16-bit (modulo–2**16) error counter for each BI-
SYNC controller. It can be initialized by the user when the channel is disabled. The
counter is as follows:
This bit is valid when the BCS bit is cleared. When odd parity is selected, the transmitter
will count the number of ones in the 7-bit data character. If the total is not an odd number,
then the parity bit is made equal to one to make an odd number of ones. Then, if the re-
ceiver counts an even number of ones, an error in transmission has occurred. In the same
manner, for even parity, an even number must result from the calculation performed at
both ends of the line.
When this mode is selected, the receiver expects external logic to indicate the beginning
of the data field using the CD1/L1SY1 pin, if SCC1 is used, and the CD2 and CD3 pins,
respectively, if SCC2 or SCC3 are used in this mode. In this mode, there will be no carrier
detect function for the SCC.
When the channel is programmed to work through the serial channels physical interface
(IDL or GCI) and EXSYN is set, the layer-1 logic carries out the synchronization using the
L1SY1 pin. In PCM mode, the L1SY1–L1SY0 pins are used.
In NMSI mode, the CD pins (and the CD timing) are used to synchronize the data. CD
should be asserted on the second data bit of the frame when used as a sync.
PM
15
—PAREC—Parity Error Counter (on received characters)
0 = Odd Parity
1 = Even Parity
buffer and sets the PR bit in the BD. The channel terminates message reception, clos-
es the buffer, sets the PR bit in the BD, and generates the RX interrupt (if enabled).
The channel also increments the parity error counter (PAREC), and the receiver then
enters hunt mode immediately.
acter is received, with a byte delay (eight serial clocks) between the status update and
the CRC calculation. When using control character recognition to detect the end of the
block and cause the checking of the CRC that follows, the channel closes the buffer,
sets the CR bit in the BD, and generates the RX interrupt (if enabled).
EXSYN
14
NTSYN
13
REVD
12
BCS
11
MC68302 USER’S MANUAL
10
—
RTR
9
RBCS
8
SYNF
7
Communications Processor (CP)
ENC
6
COMMON SCC MODE BITS
5
4-91
0