MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 112

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
3.8.7.2.2 Lowest Power Mode
In this mode, the processor frequency can be further reduced beyond the minimum system
frequency limit (e.g., lower than the limit of 8 MHz). In this mode, the LPREC bit must be set
to one by the user, causing the M68000 core to be reset as the lowest power mode is exited.
The M68000 core is given an internal reset sequence for 16 to 32 clock cycles, and execu-
tion resumes with the fetching of the reset vector. The RESET pin does not externally assert
during the internal reset sequence. The entire M68000 core status is lost in this mode (A0–
A7, D0–D7, PC, SR, etc.); however, the IMP peripheral status is retained (this includes the
dual-port RAM, internal registers, BAR, etc.).
3.8.7.2.3 Lowest Power Mode with External Clock
After the IMP is safely in the lowest power mode the EXTAL frequency can be externally re-
duced to a lower frequency. In this mode, the clock dividing should not be done in the LPCD
bits, but rather externally on the EXTAL pin.
The major difference in this mode, is that the entire IMP is now running at a lower clock rate.
Any IMP on-chip peripherals and any bus cycles executed by one of the on-chip masters are
thus slowed down.
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The following list gives a step-by-step example of how to use the lowest power mode. For
this example, an external wakeup signal is issued to the PB11 pin to exit the lowest power
mode.
1. Set the lower byte of the SCR (location $F7) to $FF. This sets the LPREC bit, the
2. Disable all interrupts except PB11 in the IMR.
3. Turn off any unneeded peripherals, such as the SCCs, by clearing the ENR and ENT
4. Execute the STOP instruction. Lowest power mode is now entered.
5. A wakeup signal comes from the system to the PB11 pin.
6. The IMP then generates the PB11 interrupt and a reset is automatically generated to
7. After the IMP is reset, software processing continues from the exception vector table
LPEN bit, and sets the clock divider to its maximum value (divide by 1024).
bits. Also turn off any unneeded baud rate generators by setting the EXTC bits in the
SCON registers. This procedure can save as much as 4 mA per SCC at 16.67 MHz.
(EXTC is cleared by default after reset.)
the M68000 core.
reset vector address. The M68000 is reset, but the rest of the IMP retains its state.
The input to EXTAL must be greater than or equal to 25kHz.
The use of external clocks with the SCCs allows the original se-
rial rates to be maintained; however, before attempting this, the
SCC performance data should be carefully reviewed (see Ap-
MC68302 USER’S MANUAL
NOTE
NOTE
MOTOROLA