MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 54

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
(DAPR), an 8-bit function code register (FCR), a 16-bit byte count register (BCR), a 16-bit
channel mode register (CMR), and an 8-bit channel status register (CSR). These registers
provide the addresses, transfer count, and configuration information necessary to set up a
transfer. They also provide a means of controlling the IDMA and monitoring its status. All
registers can be modified by the M68000 core. The IDMA also includes another 16-bit reg-
ister, the data holding register (DHR), which is not accessible to the M68000 core and is
used by the IDMA for temporary data storage.
3.1.2.1 Channel Mode Register (CMR)
The CMR, a 16-bit register, is reset to $0000.
Bit 15—Reserved for future use.
ECO—External Control Option
INTN—Interrupt Normal
INTE—Interrupt Error
3-4
15
—
0 = If the request generation is programmed to be external in the REQG bits, the con-
1 = If the request generation is programmed to be external in the REQG bits, the con-
0 = When the channel has completed an operand transfer without error conditions as
1 = When the channel has completed an operand transfer without error conditions as
0 = If a bus error occurs during an operand transfer either on the source read (BES) or
1 = If a bus error occurs during an operand transfer either on BES or BED, the channel
ECO
14
trol signals (DACK and DONE) are used in the source (read) portion of the transfer
since the peripheral is the source.
trol signals (DACK and DONE) are used in the destination (write) portion of the
transfer since the peripheral is the destination.
indicated by DONE, the channel does not generate an interrupt request to the IMP
interrupt controller. The DONE bit remains set in the CSR.
indicated by DONE, the channel generates an interrupt request to the IMP interrupt
controller and sets DONE in the CSR.
the destination write (BED), the channel does not generate an interrupt to the IMP
interrupt controller. The appropriate bit remains set in the CSR.
generates an interrupt to the IMP interrupt controller and sets the appropriate bit
(BES or BED) in the CSR.
INTN
An interrupt will only be generated if the IDMA bit is set in the in-
terrupt mask register (IMR).
13
INTE
12
11
REQG
10
MC68302 USER’S MANUAL
SAPI
9
DAPI
NOTE
8
7
SSIZE
6
5
DSIZE
4
3
BT
2
MOTOROLA
RST
1
STR
0