MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 98

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
Bits 12–2—Base Address Mask
For example, for a 64K-byte block, this field should be M13, M14, M15 = 0 with the rest of
the base address mask bits (M23–M16) equal to one.
After system reset, the bits of the base address mask field default to ones (selecting the
smallest block size of 8K) to allow CS0 to select the ROM device containing the reset vector.
MRW—Mask Read/Write
CFC—Compare Function Code
3.6.3 Chip Select Example
Set up chip select 2 to assert for a 1 Megabyte block of external RAM beginning at $200000
with 1 wait state. Note that the address must be on a block boundary (i.e. the starting ad-
dress of a 1 Megabyte block could not be $210000).
3-48
These bits are used to set the block size of a particular chip-select line. The address com-
pare logic uses only the address bits that are not masked (i.e., mask bit set to one) to de-
tect an address match within its block size.
After system reset, this bit defaults to zero.
After system reset, this bit defaults to one.
0 = The address bit in the corresponding BR is masked; the address compare logic
1 = The address bit in the corresponding BR is not masked; the address compare logic
0 = The RW bit in the BR is masked. The chip select is asserted for both read and write
1 = The RW bit in the BR is not masked. The chip select is asserted for read-only or
0 = The FC bits in the BR are ignored. The chip select is asserted without comparing
1 = The FC bits on the BR are compared. The address space compare logic uses the
does not use this address bit. The corresponding external address line value is a
don't care in the comparison.
uses this address bit.
operations.
write-only operations as programmed by the corresponding RW bit in BR3–BR0.
the FC bits. If the application requires the user to recognize several address spac-
es (e.g., user space without distinguishing between data and program space), FC
bits must be decoded externally.
FC bits to assert the CS line.
Do not assert DTACK externally when it is programmed to be
generated internally.
Even when CFC = 0, if the function code lines are internally or
externally generated as “111”, the chip select will not be assert-
ed.
MC68302 USER’S MANUAL
NOTE
NOTE
MOTOROLA