MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 392

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

MC68302 Applications
fully functioning MC68302s, each having an isolated bus and the ability to send data and
messages between them (e.g., through a shared RAM). However, another approach is pos-
sible.
By using the MC68302 “disable CPU logic” feature, enabled with the DISCPU pin, the
MC68302 can be converted into an intelligent slave peripheral that no longer has its M68000
core operating. The SDMA channels and IDMA channel request the bus externally through
the bus request (BR) pin. (When not in slave mode, these channels request the bus inter-
nally to the on-chip bus arbiter, with no external indication visible.) A typical slave mode ex-
ample is shown in Figure D-19. A single master MC68302 (i.e., one with the M68000 core
enabled) can access and control one or more slave MC68302s. (i.e., ones with the M68000
core disabled.)
M68000 BUS
CORE ENABLED
CORE DISABLED
CORE DISABLED
(MASTER)
(SLAVE)
(SLAVE)
MC68302 #1
MC68302 #2
MC68302 #3
PI/O
PI/O
A23
A23
5V
5V
PULL-UP RESISTORS
NOTE: A23 is not used by the slaves.
Figure D-19. Typical Slave Mode Example
Use of the “disable CPU logic” feature in a multiple MC68302 system depends mainly on the
amount of protocol processing required by the M68000 core. If the data rates are high and
the amount of protocol processing required on each channel is significant, the M68000 core
may be the limiting factor in communications performance. Thus, further increases in serial
rates will not yield additional packets/sec performance. In such a case, a faster processor
(such as the MC68020/MC68030) could be used to control all three MC68302 devices in
slave mode.
The bus utilization of the SDMA channels on the three MC68302 devices is not usually a
significant factor. For instance, if three SCC channels are running full duplex at 64 kbps, the
respective SDMA channels consume less than 1 percent of the M68000 bus. You can cal-
culate this figure for your design by determining how often a bus cycle to memory is required
D-42
MC68302 USER’S MANUAL
MOTOROLA