MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 109

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

When an external master desires to gain ownership, the standard M68000 bus arbitration
protocol should be used:
This protocol is also followed by the on-chip bus masters (IDMA, SDMA, and DRAM refresh)
except that they request the bus internally from the on-chip bus arbiter.
In the disable CPU mode, the IMP makes requests for the bus rather than granting the bus.
In such a system, the IMP functions as an external master, and the external processor (e.g.,
an MC68030) need not assert BGACK as it accesses the IMP's on-chip RAM and registers.
3.8.6 Hardware Watchdog
The hardware watchdog logic is used to assert BERR and set HWT when a bus cycle is not
terminated by DTACK and after a programmable number of clock cycles has elapsed. The
hardware watchdog logic has a 10-bit downcounter and a 4-bit prescaler. When enabled,
the watchdog timer commences counting clock cycles as AS is asserted (for internal or ex-
ternal bus masters). The count is terminated normally by the negation of AS; however, if the
count reaches zero before AS is negated, BERR will be asserted until AS is negated. The
hardware watchdog will operate with internal as well as external bus masters.
The hardware watchdog logic uses four bits in the SCR.
HWDEN—Hardware Watchdog Enable
MOTOROLA
1. Issue BR (to the IMP on-chip bus arbiter).
2. Wait for BG (from the IMP on-chip bus arbiter).
3. When BG is asserted, wait for the negation of both AS and BGACK.
4. Assert BGACK and begin external master bus cycles.
5. Negate BR (to the IMP on-chip bus arbiter), causing BG to be negated
6. Negate BGACK after the external master bus cycles have completed.
After system reset, this bit defaults to one to enable the hardware watchdog.
0 = The hardware watchdog is disabled.
1 = The hardware watchdog is enabled.
by the IMP on-chip bus arbiter.
When the IMP's BUSW pin is low causing the M68000 core to
operate as an MC68008, the BGACK signal should still be used
in bus arbitration control. On the original MC68008, the BGACK
signal was not available externally, and therefore could not be
used.
MC68302 USER’S MANUAL
NOTE
System Integration Block (SIB)
3-59