MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 253
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
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Data Length
Tx Buffer Pointer
4.5.16.10 Transparent Event Register
The SCC event register (SCCE) is referred to as the transparent event register when the
SCC is programmed as a transparent controller. It is an 8-bit register used to report events
recognized by the transparent channel and to generate interrupts. On recognition of an
event, the transparent controller sets the corresponding bit in the transparent event register.
Interrupts generated by this register may be masked in the transparent mask register.
The transparent event register is a memory-mapped register that may be read at any time.
A bit is cleared by writing a one (writing a zero does not affect a bit's value). More than one
bit may be cleared at a time. All unmasked bits must be cleared before the CP will negate
the internal interrupt request signal. This register is cleared at reset.
CTS—Clear-To-Send Status Changed
CD—Carrier Detect Status Changed
Bit 5—Reserved for future use.
TXE—Tx Error
RCH—Receive Character
BSY—Busy Condition
MOTOROLA
The data length is the number of octets that the CP should transmit from this BD's data
buffer. The data length, which should be greater than zero, may be even or odd. This val-
ue is never modified by the CP.
The transmit buffer pointer, which always points to the first byte of the associated data
buffer, may be even or odd. The buffer may reside in either internal or external memory.
A change in the status of the serial line was detected on the transparent channel. The
SCC status register may be read to determine the current status.
A change in the status of the serial line was detected on the transparent channel. The
SCC status register may be read to determine the current status.
An error (CTS lost or underrun) occurred on the transmitter channel.
A word has been received and written to the receive buffer.
A word was received and discarded due to lack of buffers. The receiver will resume re-
ception after an ENTER HUNT MODE command.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
CTS
7
CD
6
MC68302 USER’S MANUAL
—
5
TXE
NOTE
4
RCH
3
BSY
2
TX
1
Communications Processor (CP)
RX
0
4-133
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