MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 156

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
4.5.6.2 Maximum Receive Buffer Length Register (MRBLR)
Each SCC has one MRBLR that is used to define the receive buffer length for that SCC. The
MRBLR defines the maximum number of bytes that the IMP will write to a receive buffer on
that SCC before moving to the next buffer. The IMP may write fewer bytes to the buffer than
MRBLR if a condition such as an error or end of frame occurs, but it will never write more
bytes than the MRBLR value. Thus, buffers supplied by the user for use by the IMP should
always be of size MRBLR (or greater) in length.
The transmit buffers for an SCC are not affected in any way by the value programmed into
MRBLR. Transmit buffers may be individually chosen to have varying lengths, as needed.
The number of bytes to be transmitted is chosen by programming the data length field in the
Tx BD.
4.5.6.3 Receiver Buffer Descriptor Number (RBD#)
The RBD# for each SCC channel defines the next BD to which the receiver will move data
when it is in the IDLE state or defines the current BD during frame processing. The RBD# is
the BD offset from the SCC base in the Rx BD table. For Rx BD 0, RBD# = $00; for Rx BD
1, RBD# = $08, etc. Upon reset, the CP main controller sets this register to zero. The user
can change this register only after the ENR bit is clear and after the ENTER HUNT MODE
command has been issued. In most applications, this parameter will never need to be mod-
ified by the user.
4.5.6.4 Transmit Buffer Descriptor Number (TBD#)
The TBD# for each SCC channel defines the next BD from which the transmitter will move
data when it is in the IDLE state or defines the current BD during frame transmission. The
TBD# is the BD offset from the SCC base in the Tx BD table. For Tx BD 0, TBD# = $40; for
Tx BD 1, TBD# = $48, etc. Upon reset, the CP main controller sets this register to $40. The
user can change this register only after the STOP TRANSMIT command has been issued.
In most applications, this parameter will never need to be modified by the user.
4-36
MRBLR was not intended to be changed dynamically while an
SCC is operating. However, if it is modified in a single bus cycle
with one 16-bit move (NOT two 8-bit back-to-back bus cycles),
then a dynamic change in receive buffer length can be success-
fully achieved, which occurs when the CP moves control to the
next Rx BD in the table. Thus, a change to MRBLR will not have
an immediate effect. To guarantee the exact Rx BD on which the
change will occur, the user should change MRBLR only while
the SCC receiver is disabled (see 4.5.6 SCC Parameter RAM
Memory Map).
The MRBLR value should be greater than zero in all modes. In
the HDLC and transparent modes, the MRBLR should have an
even value.
MC68302 USER’S MANUAL
NOTE
NOTE
MOTOROLA