MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 242

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
ler sets its corresponding bit in this register. Interrupts generated by this register may be
masked in the V.110 mask register.
The V.110 event register is a memory-mapped register that may be read at any time. A bit
is cleared by writing a one (writing a zero does not affect a bit's value). More than one bit
may be cleared at a time. All unmasked bits must be cleared before the CP will clear the
internal interrupt request signal. This register is cleared at reset.
Bits 7–5, 0—Reserved for future use.
TXE—Tx Error
RXF—Receive Frame
BSY—Busy Condition
TX —Tx Buffer
4.5.15.10 V.110 Mask Register
The SCC mask register (SCCM) is referred to as the V.110 mask register when the SCC is
operating as a V.110 controller. It is an 8-bit read-write register that has the same bit format
as the V.110 event register. If a bit in the V.110 mask register is a one, the corresponding
interrupt in the event register will be enabled. If the bit is zero, the corresponding interrupt in
the event register will be masked. This register is cleared upon reset.
4.5.16 Transparent Controller
The transparent controller allows transmission and reception of serial data over an SCC
without any modification to that data stream. Transparent mode provides a clear channel on
which no bit-level manipulation is performed by the SCC. Any protocol run over transparent
mode is performed in software. The job of an SCC in transparent mode is to function simply
as a high-speed serial-to-parallel and parallel-to-serial converter. This mode is also referred
to as totally transparent or promiscuous operation.
There are several basic applications for transparent mode. First, some data may need to be
moved serially but requires no protocol superimposed. An example of this is voice data. Sec-
ond, some board-level applications require a serial-to-parallel and parallel-to-serial conver-
sion. Often this conversion is performed to allow communication between chips on the same
board. The SCCs on the MC68302 can do this very efficiently with very little M68000 core
intervention. Third, some applications require the switching of data without interfering with
4-122
An error (underrun) occurred on the transmitter channel.
A complete frame has been received on the V.110 channel.
A data byte was received and discarded due to lack of buffers. The receiver will automat-
ically enter hunt mode.
A buffer has been transmitted.This bit is set on the second to last bit of an 80-bit frame.
—
7
—
6
MC68302 USER’S MANUAL
—
5
TXE
4
RXF
3
BSY
2
TX
1
—
0
MOTOROLA