MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 286
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
Signal Description
5.19 PARALLEL I/O PINS WITH INTERRUPT CAPABILITY
The four parallel I/O pins with interrupt are shown in Figure 5-16.
PB11–PB8—Port B Parallel I/O pins
These four pins may be configured as a general-purpose parallel I/O ports with interrupt ca-
pability. Each of the pins can be configured either as an input or an output. When configured
as an input, each pin can generate a separate, maskable interrupt on a high-to-low transi-
tion. PB8 may also be used to request a refresh cycle from the DRAM refresh controller rath-
er than as an I/O pin. The input buffers have Schmitt triggers.
5.20 CHIP-SELECT PINS
The chip-select pins are shown in Figure 5-17.
CS0/IOUT2—Chip-Select 0/Interrupt Output 2
In normal operation, this pin functions as CS0. CS0 is one of the four active-low output pins
that function as chip selects for external devices or memory. It does not activate on access-
es to the internal RAM or registers (including the BAR, SCR, or CKCR registers).
When the M68000 core is disabled, this pin operates as IOUT2. IOUT2—IOUT0 provide the
interrupt request output signals from the IMP interrupt controller to an external CPU when
the M68000 core is disabled.
5-22
Figure 5-16. Port B Parallel I/O Pins with Interrupt
Figure 5-17. Chip-Select Pins
MC68302 USER’S MANUAL
MC68302
MC68302
CS0 / IOUT2
CS3–CS1
PB8
PB9
PB10
PB11
MOTOROLA
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