MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 79
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
(Handle events in the SCC1 Rx or Tx BD tables.)
At the end:
In example 1, the hardware clears the TIMER3 bit in the IPR during the interrupt acknowl-
edge cycle. This is an example of a handler for an interrupt source without multiple events.
In example 2, the IPR bit remains set as long as one or more unmasked event bits remain
the in the SCCE1 register. This is an example of a handler for an interrupt source with mul-
tiple events.
Note that, in both cases, it is not necessary to clear the IPR bit; however, in both cases, it is
necessary to clear the ISR bit to allow future interrupts from this source.
3.3 PARALLEL I/O PORTS
The IMP supports two general-purpose I/O ports, port A and port B, whose pins can be gen-
eral-purpose I/O pins or dedicated peripheral interface pins. Some port B pins are always
maintained as four general-purpose I/O pins, each with interrupt capability.
3.3.1 Port A
Each of the 16 port A pins are independently configured as a general-purpose I/O pin if the
corresponding port A control register (PACNT) bit is cleared. Port A pins are configured as
dedicated on-chip peripheral pins if the corresponding PACNT bit is set. An example block
diagram of PA0 is given in Figure 3-5
MOTOROLA
2. Immediately read the SCC1 event (SCCE1) register into a temporary location.
3. Decide which events in the SCCE1 will be handled in this handler and clear those bits
4. Clear the SCC1 bit in the ISR.
5. Execute RTE instruction. If any unmasked bits in SCCE1 remain at this time (either
in the SCCE1 as soon as possible.
uncleared by the software or set by the IMP during the execution of this handler), this
interrupt source will be made pending again immediately following the RTE instruction.
MC68302 USER’S MANUAL
System Integration Block (SIB)
3-29
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