MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 432

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

SCC Programming Reference
E.1.1.3.2 MRBLR—Maximum Rx Buffer Length. This16-bit parameter defines the maxi-
mum receiver buffer length for each of the eight receive buffer descriptors.
E.1.1.3.3 CRC Mask_L and CRC Mask_H. This 32-bit parameter contains the constant
values used for the 16-bit and 32-bit CRC calculation. For a 16-bit CRC, CRC_MASK_L
should be set to $F0B8 and CRC_MASK_H is not used. For a 32-bit CRC, the user should
set CRC_MASK_L = $DEBB and CRC_MASK_H = $20E3.
E.1.1.3.4 DISFC—Discard Frame Counter. This 16-bit parameter is incremented when a
frame is discarded due to lack of receive buffers.
E.1.1.3.5 CRCEC—CRC Error Counter. This 16-bit parameter is incremented when a
CRC error is detected in an incoming frame.
E.1.1.3.6 ABTSC—Abort Sequence Counter. This 16-bit parameter is incremented when
an abort sequence is detected in an incoming frame,
E.1.1.3.7 NMARC—Nonmatching Address Received Counter. This 16-bit parameter is
incremented when an error-free frame that does not match the user-defined addresses is
detected.
E.1.1.3.8 RETRC—Frame Retransmission Counter. This 16-bit parameter is incre-
mented when a frame is retransmitted due to a collision.
E.1.1.3.9 MFLR—Maximum Frame Length Register. This16-bit parameter defines the
maximum length of an incoming receive frame.
E.1.1.3.10 HMASK—HDLC Frame Address Mask. This 16-bit parameter is the user-
defined frame address mask register. A one should be written to each bit for which the
address comparison is to occur. Bits 15-8 contain the least significant address byte, and bits
7-0 contain the most significant address byte.
E.1.1.3.11 HADDR1, HADDR2, HADDR3, and HADDR4—HDLC Frame Address.
These four 16-bit parameters are the user-defined frame address registers. Bits 15-8 con-
tain the least significant address byte, and bits 7-0 contain the most significant address byte.
E.1.1.4 RECEIVE BUFFER DESCRIPTORS. Each SCC has eight receive buffer descrip-
tors. Each buffer descriptor consists of four words as shown below. Reserved bits in regis-
ters should be written as zeros.
E-10
OFFSET + 0
OFFSET +2
OFFSET +4
OFFSET +6
15
0
FC2
14
15
E
FC1
13
14
X
FC0
12
13
W
11
0
12
I
10
0
11
L
MC68360 USER’S MANUAL
10
9
0
F
—
9
RX BUFFER POINTER
8
0
DATA LENGTH
—
8
7
0
—
7
FC2
6
—
6
FC1
5
LG
5
FC0
4
NO
4
3
0
AB
3
2
0
CR
2
MOTOROLA
1
0
OV
1
CD
0
0
0