MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 26
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Price
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MC68302EH16C
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MC68302EH16CB1
Manufacturer:
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Quantity:
10 000
Company:
Part Number:
MC68302EH16CR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 26 of 481
- Download datasheet (2Mb)
General Description
1.3 MC68302 SYSTEM ARCHITECTURE
Most general-purpose microprocessor-based systems use an architecture that interfaces all
peripheral devices directly onto a single microprocessor bus (see Figure 1-2).
The MC68302 microprocessor architecture is shown in Figure 1-3. In this architecture, the
peripheral devices are isolated from the system bus through a dual-port memory. Various
parameters and counters and all memory buffer descriptor tables reside in the dual-port
RAM. The receive and transmit data buffers may be located in the on-chip RAM or in the off-
chip system RAM. Six DMA channels are dedicated to the six serial ports (receive and trans-
mit for each of the three SCC channels). If data for an SCC channel is programmed to be
located in the external RAM, the CP will program the corresponding DMA channel for the
required accesses, bypassing the dual-port RAM. If data resides in the dual-port RAM, then
the CP accesses the RAM with one clock cycle and no arbitration delays.
1-4
—SCP for Synchronous Communication
—Two Serial Management Controllers (SMCs) To Support IDL and GCI Auxiliary
Channels
SYSTEM BUS
Nonmultiplexed Serial Interface (NMSI) Implementing Standard Modem Signals
Figure 1-2. General-Purpose Microprocessor System Design
DMA
CPU
MC68302 USER’S MANUAL
CHANNELS
DMA AND/
OR FIFOs
SERIAL
ROM
TIMERS
CPU I/F
RAM
ADDITIONAL
DEVICES
MOTOROLA
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