MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 301
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
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Part Number:
MC68302EH16CR2
Manufacturer:
Freescale Semiconductor
Quantity:
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 301 of 481
- Download datasheet (2Mb)
6.9 AC ELECTRICAL SPECIFICATIONS—DMA
MOTOROLA
NOTES:
1. DREQ is sampled on the falling edge of CLK in cycle steal and burst modes.
2. If #80 is satisfied for DREQ, #81 may be ignored.
3. BR will not be asserted while BG, HALT, or BERR is asserted.
4. Specifications are for DISABLE CPU mode only.
5. DREQ, DACK, and DONE do not apply to the SDMA channels.
6. DMA and SDMA read and write cycle timing is the same as that for the M68000 core.
Num.
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
DREQ Asynchronous Setup Time (see Note
1)
DREQ Width Low (see Note 2)
DREQ Low to BR Low (see Notes 3 and 4)
Clock High to BR Low (see Notes 3 and 4)
Clock High to BR High Impedance (see
Notes 3 and 4)
BGACK Low to BR High Impedance (see
Notes 3 and 4)
Clock High to BGACK Low
AS and BGACK High (the Latest One) to
BG Low to BGACK Low (No Other Bus
Master) (see Notes 3 and 4)
BR High Impedance to BG High (see Notes 3
and 4)
Clock on which BGACK Low to Clock on
which AS Low
Clock High to BGACK High
Clock Low to BGACK High Impedance
Clock High to DACK Low
Clock Low to DACK High
Clock High to DONE Low (Output)
Clock Low to DONE High Impedance
DONE Input Low to Clock Low (Asynchro-
nous Setup)
BGACK Low (when BG Is Asserted)
Characteristic
MC68302 USER’S MANUAL
t
t
Symbol
t
t
t
t
REQLBRL
t
t
t
t
CLBKLAL
BRHBGH
t
t
t
t
CHACKL
CLACKH
t
t
DNLTCH
BKLBRZ
ABHBKL
BGLBKL
t
REQASI
t
CHBRL
CHBRZ
CHBKH
CHDNL
CHBKL
CLBKZ
CLDNZ
REQL
Min
16.67 MHz
1.5
1.5
15
—
—
—
30
—
—
—
—
—
—
—
15
2
0
2
(see Figure 6-6 and Figure 6-7)
Max
+30
+30
2.5
2.5
30
30
30
30
15
30
30
30
30
—
—
—
—
—
2
2
Min
1.5
1.5
15
25
15
—
—
—
—
—
—
—
—
—
—
2
0
2
20 MHz
Electrical Characteristics
Max
+25
+25
2.5
2.5
25
25
25
25
15
25
25
25
25
—
—
—
—
—
2
2
Min
1.5
1.5
10
20
10
—
—
—
—
—
—
—
—
—
—
2
0
2
25 MHz
Max
+20
+20
2.5
2.5
20
20
20
20
10
20
20
20
20
—
—
—
—
—
2
2
Unit
clks
clks
clks
clks
clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6-13
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