MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 44
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
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- Download datasheet (2Mb)
MC68000/MC68008 Core
CFC—Compare Function Code
Bits 11–0—Base Address
2.8 MC68302 MEMORY MAP
The following tables show the additional registers added to the M68000 to make up the
MC68302. All of the registers are memory-mapped. Four entries in the M68000 exception
vectors table (located in low RAM) are reserved for addresses of system configuration reg-
isters (see Table 2-6) that reside on-chip. These registers have fixed addresses of $0F0–
$0FF. All other on-chip peripherals occupy a 4K-byte relocatable address space. When an
on-chip register or peripheral is accessed, the internal access (IAC) pin is asserted.
The internal 1176-byte dual-port RAM has 576 bytes of system RAM (see Table 2-7) and
576 bytes of parameter RAM (see Table 2-8).
The parameter RAM contains the buffer descriptors for each of the three SCC channels, the
SCP, and the two SMC channels. The memory structures of the three SCC channels are
2-14
The high address field is contained in bit 11–0 of the BAR. These bits are used to set the
starting address of the dual-port RAM. The address compare logic uses only the most sig-
nificant bits to cause an address match within its block size.
0 = The FC bits in the BAR are ignored. Accesses to the IMP 4K-byte block occur with-
1 = The FC bits in the BAR are compared. The address space compare logic uses the
out comparing the FC bits.
FC bits to detect address matches.
*
Reset only upon a total system reset.
Address
Base + 23F
Base + 3FF
Base + 000
$0F2
$0F4
$0FC
Base +240
$0F0
$0FA
$0F8
Address
•
•
•
•
•
•
*
*
Table 2-6. System Configuration Register
Name
CKCR
RES
BAR
SCR
RES
RES
576 Bytes
Width
Table 2-7. System RAM
MC68302 USER’S MANUAL
Width
16
16
32
16
16
32
Reserved
Base Address Register
System Control Register
Reserved
Clock Control Register
Reserved
Block
RAM
Description
User Data Memory
(Not Implemented)
Description
Reserved
Reset Value
0000 0F00
BFFF
0000
MOTOROLA
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