MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 72

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

System Integration Block (SIB)
Option 2. The external peripheral can generate the vector. In this case the external device
must decode the interrupt acknowledge cycle, put out the 8-bit vector, and generate DTACK.
The decoding of the interrupt acknowledge cycle can be provided by the IACK7, IACK6, and
IACK1 signals (enabled in the PBCNT register) if either normal or dedicated mode is cho-
sen. These signals eliminate the need for external logic to perform the decoding of the A19–
A16, A3–A1, and FC2–FC0 pins externally to detect the interrupt acknowledge cycle. If the
IACK signals are not needed, they can be regained as general purpose parallel I/O pins. The
external device must generate DTACK in this mode, and DTACK is an input to the IMP.
Option 3. The external peripheral can assert the AVEC pin to cause the M68000 to use an
autovector. In this case, DTACK should not be asserted by the external device. AVEC is rec-
ognized by the M68000 core on the falling edge of S4 and should meet the asynchronous
setup time to the falling edge of S4. The IACK signals can be used to help generate the
AVEC signal for priority levels 1, 6, and 7, if needed.
When the IMP generates the vector, the following procedure is used. The three most signif-
icant bits of the interrupt vector number are programmed by the user in the GIMR. These
three bits are concatenated with five bits generated by the interrupt controller to provide an
8-bit vector number to the core. The interrupt controller's encoding of the five low-order bits
of the interrupt vector is shown in Table 3-5. An example vector calculation is shown in Fig-
ure 3-4. When the core initiates an interrupt acknowledge cycle for level 4 and there is no
internal interrupt pending, the interrupt controller encodes the error code 00000 onto the five
low-order bits of the interrupt vector.
3-22
If AVEC is asserted during an interrupt acknowledge cycle, an
autovector is taken, regardless of the vector on the bus. AVEC
should not be asserted during level 4 interrupt acknowledge cy-
cles.
MC68302 USER’S MANUAL
NOTE
MOTOROLA