MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 335

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

APPENDIX A
SCC PERFORMANCE
The MC68302 at 16.67 MHz was originally designed to support unrestricted operation of
multiple (three) serial communications controllers (SCCs) servicing differing communica-
tions protocols with cost-effective usage of silicon at data rates of 256 kbps for HDLC-
framed or transparent data handling and 128 kbps for BISYNC, DDCMP, V.110, or asyn-
chronous framed data. The resultant design has exceeded these design goals.
Since the MC68302 serial channels will likely service serial channels time-division multi-
plexed into higher bandwidth channels, such as the U.S. and Japanese T1 and European
CEPT primary rate channels, the physical clocking of the serial channels can be accom-
plished at the higher speeds required by these channels—up to a maximum of 40% (a 1:2.5
ratio) of the system clock frequency. This gives up to a 6.67-MHz serial clock for a 16.67-
MHz IMP system clock. At this same 16.67-MHz system clock speed, the MC68302 can
therefore handle the 1.544-MHz and 2.048-MHz clocking frequencies of T1 and CEPT lines
as well as the 4.096-Mbps signaling rates of the common ISDN interchip local buses, such
as IDL and GCI (also known as IOM-2).
Thus, the MC68302 is well equipped to handle, for instance, three 256-kbps channels mul-
tiplexed on a T1 or CEPT primary rate channel.
Where an application requires even higher bandwidth channels, such as the 384-kbps H0
channels, the 1.536-Mbps H11 channel, or higher, the following restriction should be ob-
served: bus latency of the SDMA must be less than 20 system clocks. (The BCLR signal
may be helpful here.)
If the above restriction is adhered to, the following table shows experimental performance
data obtained with the device.
The frequency ratio stated represents the system (EXTAL) frequency to serial bit rate fre-
quency. A user exceeding this bit rate will begin to experience SCC underruns and/or over-
runs. Some users may wish to tolerate an occasional underrun/overrun to slightly increase
performance.
16.67 MHz can support an MC68302 serial rate of 1.67 Mbps. Typically, this 1.67-Mbps rate
would be achieved with 1 bit every 1.67-MHz serial clock. However, it may also be achieved
MOTOROLA
For example, a ratio of 1:10 in the following table shows that an MC68302 system clock of
A previous revision of this manual showed two additional restric-
tions which have now been eliminated.
MC68302 USER’S MANUAL
NOTE
A-1