MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 189

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

ceeds the length of the data buffer, the HDLC controller will fetch the next BD in the table
and, if it is empty, will continue to transfer the rest of the frame to this BD's associated data
buffer.
During this process, the HDLC controller will check for a frame that is too long. When the
frame ends, the CRC field is checked against the recalculated value and is written to the
data buffer starting with the first address byte. The data length written to the last BD in the
HDLC frame is the length of the entire frame. This enables HDLC protocols that “lose”
frames to correctly recognize the frame-too-long condition. The HDLC controller then sets
the last buffer in frame bit, writes the frame status bits into the BD, and clears the empty bit.
The HDLC controller next generates a maskable interrupt, indicating that a frame has been
received and is in memory. The HDLC controller then waits for a new frame. Back-to-back
frames may be received with only a single shared flag between frames. Also, flags that
share a zero will be recognized as two consecutive flags.
4.5.12.3 HDLC Memory Map
When configured to operate in HDLC mode, the IMP overlays the structure shown in Table
4-7 onto the protocol-specific area of that SCC parameter RAM. Refer to 2.8 MC68302
Memory Map for the placement of the three SCC parameter RAM areas and to Table 4-2 for
the other parameter RAM values.
4.5.12.4 HDLC Programming Model
The M68000 core configures each SCC to operate in one of four protocols by the MODE1–
MODE0 bits in the SCC mode register (SCM). MODE1–MODE0 = 00 selects HDLC mode.
MOTOROLA
SCC Base + 9C
SCC Base + 9E
SCC Base + A0 #
SCC Base + A2 #
SCC Base + A4
SCC Base + A6
SCC Base + A8 #
SCC Base + AA #
SCC Base + AC #
SCC Base + AE #
SCC Base + B0 #
SCC Base + B2 #
SCC Base + B4
SCC Base + B6 #
SCC Base + B8 #
SCC Base + BA #
SCC Base + BC #
SCC Base + BE #
# Initialized by the user (M68000 core).
Address
An incorrect initialization of C_MASK may be used to “force” re-
ceive CRC errors for software testing purposes. The transmit
CRC will not be affected.
C_MASK_H
C_MASK_L
RCRC_H
TCRC_H
MAX_cnt
HADDR1
HADDR2
HADDR3
HADDR4
RCRC_L
TCRC_L
NMARC
CRCEC
HMASK
RETRC
ABTSC
Table 4-8. HDLC-Specific Parameter RAM
Name
DISFC
MFLR
MC68302 USER’S MANUAL
Width
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
NOTE
Temp Receive CRC Low
Temp Receive CRC High
Constant ($F0B8 16-Bit CRC, $DEBB 32-Bit CRC)
Constant ($XXXX 16-Bit CRC, $20E3 32-Bit CRC)
Temp Transmit CRC Low
Temp Transmit CRC High
Discard Frame Counter
CRC Error Counter
Abort Sequence Counter
Nonmatching Address Received Counter
Frame Retransmission Counter
Max Frame Length Register
Max_Length Counter
User-Defined Frame Address Mask
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
User-Defined Frame Address
Communications Processor (CP)
Description
4-69