MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 430
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 430 of 481
- Download datasheet (2Mb)
SCC Programming Reference
E.1.1.2.3 SCC Data Synchronization Register (DSR). This 16-bit register is located at off-
set $886 (SCC1), $896 (SCC2), and $8A6 (SCC3). The DSR specifies the pattern used for
the frame synchronization procedure. For HDLC, the DSR should be set to $7E7E. The DSR
value after reset is $7E7E.
E.1.1.2.4 HDLC Event Register (SCCE). This 8-bit register is located at offset $888
(SCC1), $898 (SCC2), and $8A8 (SCC3) on D15-D8 of a 16-bit data bus. The SCCE is used
to report events recognized by the HDLC channel. Bits mst be cleared by the user to avoid
missing interrupt events. Bits are cleared by writing ones to the corresponding bit positions
.
CTS—Clear-To-Send Status Changed
CD—Carrier Detect Status Changed
IDL—IDLE Sequence Status Changed
TXE—Tx Error
RXF—Rx Frame
BSY—Busy Condition
TXB—Tx Buffer
E-8
15
0 = No interrupt.
1 = A change in the status of CTS was detected.
0 = No interrupt.
1 = A change in the status of CD was detected.
0 = No interrupt.
1 = A change in the status of the receive data serial line was detected.
0 = No interrupt
1 = An error (CTS lost or underrun) occurred on the transmitter channel.
0 = No interrupt.
1 = A complete frame has been received on the HDLC channel.
0 = No interrupt.
1 = A frame was received and discarded due to lack of buffers.
0 = No interrupt.
1 = A buffer has been transmitted on the HDLC channel (set only if the I bit in the Tx
buffer descriptor is set).
SYN2
CTS
7
CD
6
MC68360 USER’S MANUAL
IDL
5
TXE
8
4
RXF
7
3
BSY
2
TXB
1
RXB
0
SYN1
MOTOROLA
0
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