MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 180

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
I—Interrupt
The following bits contain status information written by the CP after it has finished receiving
data in the associated data buffer.
C—Control Character
A—Address
M—Address Match
ID—Buffer Closed on Reception of Idles
Bits 7–6, 2—Reserved for future use.
BR—Break Received
FR—Framing Error
PR—Parity Error
OV—Overrun
4-60
This bit is meaningful only if the A bit (bit 10) is set and UM1–UM0 = 11 in the UART mode
register. Following an address match, this bit defines which address character matched
the user-defined address character, enabling the UART to receive the data.
The buffer was closed due to the reception of the programmable number of consecutive
IDLE sequences (defined in MAX_IDL).
A break sequence was received while receiving data into this buffer.
A character with a framing error was received and is located in the last byte of this buffer.
A framing error is detected by the UART controller when no stop bit is detected in the re-
ceive data string.
A character with a parity error was received and is located in the last byte of this buffer.
A receiver overrun occurred during message reception.
0 = No interrupt is generated after this buffer has been filled.
1 = The RX bit in the UART event register will be set when this buffer has been com-
0 = This buffer does not contain a control character.
1 = This buffer contains a user-defined control character in the last byte location.
0 = The buffer contains data only.
1 = When working in nonautomatic multidrop mode (UM1–UM0 = 01), this bit indicates
0 = The address-matched user-defined UADDR2
1 = The address-matched user-defined UADDR1
pletely filled by the CP, indicating the need for the M68000 core to process the buff-
er. The RX bit can cause an interrupt.
that the first byte of this buffer contains an address byte. The address comparison
should be implemented in software. In automatic multidrop mode, this bit indicates
that the BD contains a message received immediately following an address recog-
nized in UADDR1 or UADDR2. This address is not written into the receive buffer.
MC68302 USER’S MANUAL
MOTOROLA