MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 373

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

D.5 INDEPENDENT DMA IN THE MC68302
Moving of data between a high-speed peripheral controller and memory is optimized when
a direct memory access (DMA) controller is used. The MC68302 contains an independent
direct memory access (IDMA) controller. Engineers developing system architectures requir-
ing both the M68000 microprocessor and DMA can use the MC68302 to obtain both building
blocks in one package.
The registers associated with the programming of the IDMA are as follows: six IDMA regis-
ters, four interrupt controller registers, and one parallel l/O register (see Table D-1).
D.5.1 IDMA Overview
The IDMA can transfer data between any combination of memory and l/O, in either byte or
word quantities with even or odd source and destination addresses. Each IDMA transfer re-
quires two fundamental operations: reading data from a source address and writing data to
a destination address. A pointer to the source data is contained in the source address point-
MOTOROLA
REINIT0 MOVEA.L
*Bad Status:
BSTAT
*Note that the UART FRMEC, NOSEC, and PAREC counters record bad status.
* Almost Done:
ALMDONE
END
BSET.B
BTST.B
BNE.B
ADDA.W
BRA.B
BRA.B
NOP
BRA.B
MOVE.W
RTE
Acronym
PACNT
DAPR
SAPR
GIMR
CMR
BCR
CSR
FCR
IMR
IPR
ISR
#$07,(A0)
#$05,(A0)
REINIT0
#$08,A0
ALMDONE
#$700600,A0
ALMDONE
INCPTR
#$0100,1SR
Channel Mode Register
Source Address Pointer Register
Destination Address Pointer Register
Byte Count Register
Channel Status Register
Function Code Register
Global Interrupt Mode Register
Interrupt Pending Register
Interrupt Mask Register
Interrupt In-Service Register
Port A Control Register
Table D-1. IDMA Registers
MC68302 USER’S MANUAL
Register
;Set Empty bit of Rx BD
;test Wrap bit
;It set, reinit A0 to 700600
;else inc A0 by 8 to next Rx BD
;Jump to Almost Done
;Reinitialize A0
;Jump to almost Done
;Bad status handler would go here
;Jump back to Receive handler
;Clear SCC3 bit in the ISR
;end of interrupt handler
Base + $802
Base + $804
Base + $808
Base + $80e
Base + $810
Base + $812
Base + $814
Base + $816
Base + $818
Base + $81e
Base + $80c
Address
MC68302 Applications
D-23