MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 149
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 149 of 481
- Download datasheet (2Mb)
MOTOROLA
(OUTPUT)
(OUTPUT)
NOTE: A "frame" includes opening and closing flags in HDLC and SYNCs in BISYNC and DDCMP.
(OUTPUT)
(OUTPUT)
NOTE: A "frame" includes opening and closing flags, SYNCs, etc.
(INPUT)
(INPUT)
TCLK
(I/O)
RTS
CTS
TXD
TCLK
TXD
RTS
CTS
(I/O)
allel I/O lines in the PACNT register. To cause the TXD and RTS pins to simply
remain high in NMSI1, NMSI2, and NMSI3 modes, use this loopback mode in con-
junction with setting the SDIAG1–SDIAG0 bits in the SIMODE register to loop-
back control.
Figure 4-13. Output Delays from RTS Low, Synchronous Protocol
Figure 4-14. Output Delays from CTS Low, Synchronous Protocol
If an internal loopback is desired when this SCC is configured to a multiplexed
physical interface, then only the SDIAG1–SDIAG0 bits need be set.
When using loopback mode, the clock source for the transmitter and the receiver
(as set in the TCS and RCS bits in the SCON register), must be the same. Thus,
DATA READY TO TRANSMIT HERE
3.5 TCLKS
FIRST BIT OF DATA IN FRAME
CTS SAMPLED AS LOW HERE
MC68302 USER’S MANUAL
FIRST BIT OF FRAME
LAST BIT OF FRAME DATA
LAST BIT OF FRAME
Communications Processor (CP)
CTS MUST NOT BE NEGATED
UNTIL RTS IS NEGATED,
OR A CTS LOST ERROR
WILL RESULT.
4-29
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