MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 42
MC68302EH16C
Manufacturer Part Number
MC68302EH16C
Description
IC MPU MULTI-PROTOCOL 132-PQFP
Manufacturer
Freescale Semiconductor
Datasheets
1.MC68302AG20C.pdf
(4 pages)
2.MC68302AG20C.pdf
(2 pages)
3.MC68302AG20C.pdf
(13 pages)
4.MC68302EH16C.pdf
(481 pages)
Specifications of MC68302EH16C
Processor Type
M683xx 32-Bit
Speed
16MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-MQFP, 132-PQFP
Controller Family/series
68K
Core Size
32 Bit
Ram Memory Size
1152Byte
Cpu Speed
16MHz
No. Of Timers
3
Embedded Interface Type
SCP, TDM
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
16MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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- MC68302AG20C PDF datasheet
- MC68302AG20C PDF datasheet #2
- MC68302AG20C PDF datasheet #3
- MC68302EH16C PDF datasheet #4
- Current page: 42 of 481
- Download datasheet (2Mb)
MC68000/MC68008 Core
2.7 MC68302 IMP CONFIGURATION CONTROL
Four reserved entries in the external M68000 exception vector table (see Table 2-5) are
used as addresses for internal system configuration registers. These entries are at locations
$0F0, $0F4, $0F8, and $0FC. The first entry is the on-chip peripheral base address register
(BAR) entry; the second is the on-chip system control register (SCR) entry; the least signif-
icant word of the third entry is the clock control register (CKCR), and fourth entry is reserved
for future use.
The BAR entry contains the BAR described in this section. The SCR entry contains the SCR
described in 3.8.1 System Control Register (SCR). The CKCR entry contains the CKCR reg-
ister described in 3.9 Clock Control Register.
Figure 2-5 shows all the MC68302 IMP on-chip addressable locations and how they are
mapped into system memory.
The on-chip peripherals, including those peripherals in both the CP and SIB, require a 4K-
byte block of address space. This 4K-byte block location is determined by writing the intend-
ed base address to the BAR in supervisor data space (FC = 5). The address of the BAR en-
2-12
BASE + $400
BASE + $800
BASE + $FFF
BASE + $0
Figure 2-5. MC68302 IMP Configuration Control
$0F0
$0F4
$0F8
$0FC
MC68302
PARAMETER RAM
SYSTEM RAM
(DUAL-PORT)
(DUAL-PORT)
4K BLOCK
SCR ENTRY
BAR ENTRY
CKCR ENTRY
RESERVED
REGISTERS
INTERNAL
MC68302 USER’S MANUAL
BAR
POINTS
$xxx000 = BASE
TO THE
BASE
$FFFFFF
$3FF
$0
SYSTEM MEMORY MAP
256 VECTOR
EXCEPTION
4K BLOCK
ENTRIES
VECTOR
TABLE
MOTOROLA
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