MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 111

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

At the end of the STOP instruction, a major change to the IMP occurs. The M68000 core
immediately goes into a standby state in which it executes no instructions. In this state, the
clock internally sent to the M68000 core is internally divided, saving power. The amount of
this divide ratio is configured by the user. At the same time, however, the rest of the IMP
continues to operate at the normal system frequency (i.e., the frequency on the EXTAL pin).
All peripherals continue to operate normally during this time. Also, during low-power modes,
all IMP external signals continue to function normally and at full speed.
In all modes, any of the 16 possible internal interrupt request (INRQ) sources can cause the
IMP to leave a low-power mode. Masked interrupt sources will never cause a lower power
mode to be exited. If it is desired to have an external signal cause the IMP to exit a low-pow-
er mode, it must be routed to one of the PB11–PB8 port pins with interrupt capability, so that
an INRQ interrupt can be generated.
There are three low-power modes: low power, lowest power, and lowest power with external
clock. Low-power mode allows execution to resume immediately upon recognition of the in-
terrupt, with no loss of any IMP state information. Lowest power mode requires execution to
resume with an internal M68000 reset. The M68000 state is lost, but the rest of the IMP pe-
ripheral states are completely retained. The lowest power mode with external clock offers
the absolute minimum power consumption with the IMP, but requires external hardware.
3.8.7.2.1 Low-Power Mode
This mode is possible if the user-selected low-power frequency applied to the M68000 core
remains above the operating limits specified in Section 6 Electrical Characteristics (e.g., 8
MHz). In this mode, LPREC is set to zero. Once an INRQ interrupt becomes pending, the
system control block switches the M68000 core back to full frequency and power, and be-
gins handling the interrupt in the usual manner. No M68000 core or peripheral status is lost
in this mode. Note: The CLKO signal will remain at the same frequency that is on the EXTAL
input.
The following list gives a step-by-step example of how to use the low-power mode. For this
example, an interrupt from either timer 1 or timer 2 causes the IMP to exit the low-power
mode. This example also assumes an initial operating frequency of 16.67 MHz for the IMP.
MOTOROLA
1. Set the lower byte of the SCR (location $F7) to $20. This sets the LPEN bit and sets
2. Disable all interrupts except TIMER1 and TIMER2 in the IMR.
3. Turn off any unneeded peripherals, such as the SCCs, by clearing the ENR and ENT
4. Execute the STOP instruction. The low-power mode is now entered.
5. When a timer 1 or 2 interrupt occurs, the M68000 resumes execution with the timer 1
the clock divider to a value of 2 (divide by 2).
bits. Also turn off any unneeded baud rate generators by setting the EXTC bits in the
SCON registers. This procedure can save as much as 4 mA per SCC at 16.67 MHz.
(EXTC is cleared by default on power-on reset.)
or 2 interrupt handler. After the RTE instruction, execution continues with the instruc-
tion following the STOP instruction in step 4 above. All IMP state information is re-
tained.
MC68302 USER’S MANUAL
System Integration Block (SIB)
3-61