MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 425

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

E.1.1.1 COMMUNICATIONS PROCESSOR (CP) REGISTERS. The CP has one set of
three registers that configure the operation of the serial interface for all three SCCs. These
registers are discussed in the following paragraphs.
E.1.1.1.1 Command Register CR). The command register is an 8-bit register located at
offset $860 (on D15-D8 of a 16-bit data bus). This register is used to issue commands to the
CP. The user should set the FLG bit when a command is written to the command register.
The CP clears the FLG bit during command processing to indicate that it is ready for the next
command. Reserved bits in registers should be written as zeros.
RST—Software Reset Command (set by the user and cleared by the CP)
GCI—GCI Commands
MOTOROLA
NOTE: The offset is from the MC68302 base address + ($880 for SCC1, $890 for SCC2, or $8A0 for SCC3).
NOTE: The offset is from the MC68302 base address.
Initialized
Initialized
by User
by User
Yes
Yes
Yes
Yes
Yes
Yes
Yes
0 = No software reset command issued or cleared by CP during software reset se-
1 = Software reset command (FLG bit should also be set if it is not already set).
0 = Normal operation.
1 = The OPCODE bits are used for GCI commands (user should set CH. NUM. to 10
quence.
and FLG to 1).
Offset
Offset
Hex
Hex
8B2
8B4
860
0A
0C
0E
00
02
04
06
08
Reserved
SCC Configuration Register (SCON)
SCC Mode Register (SCM)
SCC Data Synchronization Register (DSR)
Event Register (SCCE)
Mask Register (SCCM)
Status Register (SCCS)
Reserved
Command Register (CR)
Serial Interface Mask Register (SIMASK)
Serial Interface Mask Register (SIMODE)
Table E-1 (d).General Registers (Only One Set)
RST
7
Table E-1 (c) SCCx Register Set
GCI
6
MC68360 USER’S MANUAL
5
OPCODE
4
—
3
Name
Name
CH. NUM.
2
Reserved
Reserved
Reserved
Reserved
1
FLG
SCC Programming Reference
0
E-3