MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 162

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
Totally Transparent (Promiscuous) Mode
4.5.10 Disabling the SCCs
If an SCC transmitter or receiver is not needed for a period of time or a mode change is re-
quired, then it may be disabled and re-enabled later. In this case, a sequence of operations
is followed.
For the SCC transmitter, the sequence is as follows:
For the SCC receiver, the sequence is as follows:
This sequence assures that any buffers in use will be properly closed and that new data will
be transferred to/from a new buffer.
While an SCC is disabled (and only while an SCC is disabled) the SCON and SCM registers
may be modified. Thus, once disabled, changes such as the SCC protocol, diagnostic mode,
or baud rate may be made. Such parameters cannot be modified “on-the-fly.” The DSR
should also only be modified while an SCC is disabled, although an exception exists to this
in the UART mode concerning the transmission of partial stop bits.
The TBD# and RBD# values in the parameter RAM are not reset by the disabling process;
thus, the very next BDs will be used when the SCC is re-enabled. A full software reset of the
entire CP including the three SCCs is accomplished in the command register (CR). To reset
an SCC to its initial state, the RX internal state, the TX internal state, the TBD#, and the
RBD# can be written to their values after reset. The user can read these values for each
SCC after a reset.
4-42
The MC68302 can both receive and transmit the entire serial bit stream transparently. See
4.5.16 Transparent Controller for details.
STOP TRANSMIT Command
Wait for the FIFO to empty
Clear ENT
RESTART TRANSMIT Command
Set ENT
Clear ENR
ENTER HUNT MODE Command
Set ENR
•
• (The SCC transmitter is now disabled)
•
•
• (The SCC receiver is now disabled)
•
MC68302 USER’S MANUAL
MOTOROLA