MC68302EH16C Freescale Semiconductor, MC68302EH16C Datasheet - Page 200

• Manufacturer Part Number: MC68302EH16C
• Description: IC MPU MULTI-PROTOCOL 132-PQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68302EH16C

• Processor Type: M683xx 32-Bit
• Speed: 16MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Controller Family/series: 68K
• Core Size: 32 Bit
• Ram Memory Size: 1152Byte
• Cpu Speed: 16MHz
• No. Of Timers: 3
• Embedded Interface Type: SCP, TDM
• Digital Ic Case Style: PQFP
• Rohs Compliant: Yes
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Communications Processor (CP)
UN—Underrun
The HDLC controller encountered a transmitter underrun condition while transmitting the as-
sociated data buffer.
CT—CTS Lost
CTS in NMSI mode or L1GR (layer-1 grant) in IDL/GCI mode was lost during frame trans-
mission. If data from more than one buffer is currently in the FIFO when this error occurs,
this bit will be set in the Tx BD that is currently open.
Data Length
Tx Buffer Pointer
4.5.12.12 HDLC Event Register
The SCC event register (SCCE) is called the HDLC event register when the SCC is operat-
ing as an HDLC controller. It is an 8-bit register used to report events recognized by the
HDLC channel and to generate interrupts. Upon recognition of an event, the HDLC controller
sets its corresponding bit in the HDLC event register. Interrupts generated by this register
may be masked in the HDLC mask register.
The HDLC event register is a memory-mapped register that may be read at any time. A bit
is cleared by writing a one; writing a zero does not affect a bit's value. More than one bit may
be cleared at a time. All unmasked bits must be cleared before the CP will clear the internal
interrupt request. This register is cleared at reset.
An example of the timing of various events in the HDLC event register is shown in Figure 4-
29.
4-80
The data length is the number of octets the HDLC controller should transmit from this BD's
data buffer. It is never modified by the CP. The value of this field should be greater than
zero.
The transmit buffer pointer, which contains the address of the associated data buffer, may
be even or odd. The buffer may reside in either internal or external memory.
For correct operation of the function codes, the upper 8 bits of
the pointer must be initialized to zero.
MC68302 USER’S MANUAL
NOTE
MOTOROLA