AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 103

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

9. Secure Access Unit (SAU)
9.1
9.2
32099F–11/2010
Features
Overview
Rev 1.1.0.2
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•
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In many systems, erroneous access to peripherals can lead to catastrophic failure. An exam-
ple of such a peripheral is the Pulse Width Modulator (PWM) used to control electric motors.
The PWM outputs a pulse train that controls the motor. If the control registers of the PWM
module are inadvertently updated with wrong values, the motor can start operating out of con-
trol, possibly causing damage to the application and the surrounding environment. However,
sometimes the PWM control registers must be updated with new values, for example when
modifying the pulse train to accelerate the motor. A mechanism must be used to protect the
PWM control registers from inadvertent access caused by for example:
To improve the security in a computer system, the AVR32UC implements a Memory Protec-
tion Unit (MPU). The MPU can be set up to limit the accesses that can be performed to
specific memory addresses. The MPU divides the memory space into regions, and assigns a
set of access restrictions on each region. Access restrictions can for example be read/write if
the CPU is in supervisor mode, and read-only if the CPU is in application mode. The regions
can be of different size, but each region is usually quite large, e.g. protecting 1 kilobyte of
address space or more. Furthermore, access to each region is often controlled by the execu-
tion state of the CPU, i.e. supervisor or application mode. Such a simple control mechanism is
often too inflexible (too coarse-grained chunks) and with too much overhead (often requiring
system calls to access protected memory locations) for simple or real-time systems such as
embedded microcontrollers.
Usually, the Secure Access Unit (SAU) is used together with the MPU to provide the required
security and integrity. The MPU is set up to protect regions of memory, while the SAU is set up
to provide a secure channel into specific memory locations that are protected by the MPU.
These specific locations can be thought of as fine-grained overrides of the general coarse-
grained protection provided by the MPU.
• Errors in the software code
• Transient errors in the CPU caused by for example electrical noise altering the execution
Remaps registers in memory regions protected by the MPU to regions not protected by the
MPU
Programmable physical address for each channel
Two modes of operation: Locked and Open
path of the program
– In Locked Mode, access to a channel must be preceded by an unlock action
– In Open Mode, all channels are permanently unlocked
• An unlocked channel remains open only for a specific amount of time, if no access is
• Only one channel can be open at a time, opening a channel while another one is open
• Access to a locked channel is denied, a bus error and optionally an interrupt is
• If a channel is relocked due to an unlock timeout, an interrupt can optionally be
performed during this time, the channel is relocked
locks the first one
returned
generated
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