AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 147

MCU AVR32 32KB FLASH 48TLLGA

AT32UC3L032-D3UR

Manufacturer Part Number
AT32UC3L032-D3UR
Description
MCU AVR32 32KB FLASH 48TLLGA
Manufacturer
Atmel
Series
AVR®32 UC3r
Datasheet

Specifications of AT32UC3L032-D3UR

Core Processor
AVR
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, PWM, WDT
Number Of I /o
36
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.62 V ~ 3.6 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TLLGA
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
SPI, TWI, USART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
36
Number Of Timers
7
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
AT32UC3L-EK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 9 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
11.7
11.7.1
32099F–11/2010
Module Configuration
Interrupt Request Signal Map
The specific configuration for each INTC instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 11-2.
The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up
to 32 interrupt request signals. All interrupt signals in the same group share the same autovector
address and priority level.
The table below shows how the interrupt request signals are connected to the INTC.
Table 11-3.
Module Name
INTC
Group
0
1
2
3
4
5
6
7
8
9
INTC Clock Name
Interrupt Request Signal Map
Clock Name
CLK_INTC
Line
0
0
1
0
0
0
1
2
3
0
1
2
3
0
1
2
3
0
0
0
Module
AVR32 UC3 Core
AVR32 UC3 Core
AVR32 UC3 Core
Flash Controller
Secure Access Unit
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Peripheral DMA Controller
Power Manager
System Control Interface
Asynchronous Timer
Description
Clock for the INTC bus interface
AT32UC3L016/32/64
OCD DCEMU_DIRTY
SYSREG COMPARE
OCD DCCPU_READ
AST ALARM
FLASHCDW
PDCA 10
PDCA 11
PDCA 0
PDCA 1
PDCA 2
PDCA 3
PDCA 4
PDCA 5
PDCA 6
PDCA 7
PDCA 8
PDCA 9
Signal
SCIF
SAU
PM
147

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