AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 748

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

31.5
Table 31-9.
31.5.1
32099F–11/2010
Instruction
OPCODE
Others
0x0C
0x0F
0x1C
0x1F
0x01
0x02
0x03
0x04
0x06
0x10
0x11
0x12
0x13
0x14
0x15
0x17
JTAG Instruction Summary
Security Restrictions
JTAG Instruction Summary
SAMPLE_PRELOAD
EXTEST
CLAMP
AVR_RESET
CHIP_ERASE
NEXUS_ACCESS
MEMORY_WORD_ACCESS
MEMORY_SERVICE
MEMORY_SIZED_ACCESS
SYNC
HALT
N/A
Instruction
IDCODE
INTEST
MEMORY_BLOCK_ACCESS
CANCEL_ACCESS
BYPASS
The implemented JTAG instructions in the 32-bit AVR are shown in the table below.
When the security fuse in the Flash is programmed, the following JTAG instructions are
restricted:
For description of what memory locations remain accessible, please refer to the SAB address
map.
Full access to these instructions is re-enabled when the security fuse is erased by the
CHIP_ERASE JTAG instruction.
• Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the
• NEXUS_ACCESS
• MEMORY_WORD_ACCESS
• MEMORY_BLOCK_ACCESS
• MEMORY_SIZED_ACCESS
non-volatile memory.
Description
Select the 32-bit Device Identification register as data register.
Take a snapshot of external pin values without affecting system operation.
Select boundary-scan chain as data register for testing circuitry external to
the device.
Select boundary-scan chain for internal testing of the device.
Bypass device through Bypass register, while driving outputs from boundary-
scan register.
Apply or remove a static reset to the device
Erase the device
Select the SAB Address and Data registers as data register for the TAP. The
registers are accessed in Nexus mode.
Select the SAB Address and Data registers as data register for the TAP.
Select the SAB Data register as data register for the TAP. The address is
auto-incremented.
Cancel an ongoing Nexus or Memory access.
Select the SAB Address and Data registers as data register for the TAP. The
registers are accessed in Memory Service mode.
Select the SAB Address and Data registers as data register for the TAP.
Synchronization counter
Halt the CPU for safe programming.
Bypass this device through the bypass register.
Acts as BYPASS
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