AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 199

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

32099F–11/2010
The interrupt sources will generate an interrupt request if the corresponding bit in the Interrupt
Mask Register is set. The interrupt sources are ORed together to form one interrupt request. The
SCIF will generate an interrupt request if at least one of the bits in the Interrupt Mask Register
(IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable
Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable
Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt
Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear
Register (ICR). Because all the interrupt sources are ORed together, the interrupt request from
the SCIF will remain active until all the bits in ISR are cleared.
• BRIFARDY - Backup Register Interface Ready.
• DFLL0RCS - DFLL Reference Clock Stopped:
• DFLL0RDY - DFLL Ready:
• DFLL0LOCKLOSTA - DFLL lock lost on Accurate value:
• DFLL0LOCKLOSTF - DFLL lock lost on Fine value:
• DFLL0LOCKLOSTC - DFLL lock lost on Coarse value:
• DFLL0LOCKA - DFLL Locked on Accurate value:
• DFLL0LOCKF - DFLL Locked on Fine value:
• DFLL0LOCKC - DFLL Locked on Coarse value:
• BODDET - Brown out detection:
• SM33DET - Supply Monitor 3.3V Detector:
• VREGOK - Voltage Regulator OK:
• OSCRDY - OSCReady:
• OSC32RDY - 32KHz Oscillator Ready:
– A 0 to 1 transition on the PCLKSR.BRIFARDY bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTA bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTF bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTC bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKA bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKF bit is detected.
– A 0 to 1 transition on the PCLKSR.DFLLLOCKC bit is detected.
– A 0 to 1 transition on the PCLKSR.BODDET bit is detected.
– A 0 to 1 transition on the PCLKSR.SM33DET bit is detected.
– A 0 to 1 transition on the PCLKSR.VREGOK bit is detected.
– A 0 to 1 transition on the PCLKSR.OSCRDY bit is detected.
– A 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected.
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