AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 605

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

26.6.10
26.6.11
32099F–11/2010
ADC Conversion
Analog Compare Mode
The Sample and Hold time has to be programmed through the SHTIM field in the ADC Configu-
ration Register (ACR). This field can define a Sample and Hold time between 1 and 16
CLK_ADC cycles.
ADC conversions are performed on all enabled channels when a trigger condition is detected.
For details regarding trigger conditions see
a specific analog input pin so it can be included or excluded in an Analog-to-Digital conversion
sequence and to identify which AD pin was used to convert the current value in the Last Con-
verted Data Register (LCDR). Channel number N corresponding to AD pin number N.
Channels are enabled by writing a one to the corresponding bit in the Channel Enable Register
(CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register
(CHDR). Active channels are listed in the Channel Status Register (CHSR).
When a conversion sequence is started, all enabled channels will be converted in one sequence
and the result will be placed in the Last Converted Data Register (LCDR) with the channel num-
ber used to produce the result. It is important to read out the results while the conversion
sequence is ongoing, as new values will automatically overwrite any old value and the old value
will be lost if not previously read by the user.
If the Analog-to-Digital Converter cell is inactive when starting a conversion sequence, the con-
version logic will wait a configurable number of CLK_ADC cycles as defined in the startup time
field in the ADC Configuration Register (ACR). After the cell is activated all enabled channels is
converted one by one until no more enabled channels exist. The conversion sequence converts
each enabled channel in order starting with the channel with the lowest channel number. If the
ACR.SLEEP bit is one, the Analog-to-Digital Converter cell is deactivated after the conversion
sequence has finished.
For each channel converted, the ADCIFB waits a Sample and Hold number of CLK_ADC cycles
as defined in the SHTIM field in ACR, and then instructs the Analog-to-Digital Converter cell to
start converting the analog voltage. The ADC cell requires 10 CLK_ADC cycles to actually con-
vert the value, so the total time to convert a channel is Sample and Hold + 10 CLK_ADC cycles.
The ADCIFB can test if the converted values, as they become available, are below, above, or
inside a specified range and generate interrupt requests based on this information. This is useful
for applications where the user wants to monitor some external analog signal and only initiate
actions if the value is above, below, or inside some specified range.
The Analog Compare mode is enabled by writing a one to the Analog Compare Enable (ACE) bit
in the Mode Register (MR). The values to compare must be written to the Low Value (LV) field
and the High Value (HV) field in the Compare Value Register (CVR). The Analog Compare
mode will, when enabled, check all enabled channels against the pre-programmed high and low
values and set status bits.
To generate an interrupt request if a converted value is below a limit, write the limit to the
CVR.LV field and enable interrupt request on the Compare Lesser Than (CLT) bit by writing a
one to the corresponding bit in the Interrupt Enable Register (IER). To generate an interrupt
request if a converted value is above a limit, write the limit to the CVR.HV field and enable inter-
rupt for Compare Greater Than (CGT) bit. To generate an interrupt request if a converted value
is inside a range, write the low and high limit to the LV and HV fields and enable the Compare
Section
26.8.1. The term channel is used to identify
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