AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 487

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.9.4
Name:
Access Type:
Offset:
Reset Value:
• ACKLAST: ACK Last Master RX Byte
• PECEN: Packet Error Checking Enable
• NBYTES: Number of data bytes in transfer
• VALID: CMDR Valid
• STOP: Send STOP condition
• START: Send START condition
• REPSAME: Transfer is to same address as previous address
32099F–11/2010
VALID
31
23
15
7
-
Writing this bit to zero causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the
standard way of ending a master receiver transfer.
Writing this bit to one causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for
performing linked transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is
needed when more than 255 bytes are to be received in one single transmission.
Writing this bit to zero causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit
transmitted or received. Must be used if SMBus mode is disabled.
Writing this bit to one causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if
master receiver) will be performed.
The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is
transmitted if CMDR.STOP is set. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, ie there are NBYTES-1
data bytes and a PEC byte.
Writing this to zero indicates that CMDR does not contain a valid command.
Writing this to one indicates that CMDR contains a valid command. This bit is cleared when the command is finished.
Write this bit to zero to not transmit a STOP condition after the data bytes have been transmitted.
Write this bit to one to transmit a STOP condition after the data bytes have been transmitted.
Write this bit to zero if the transfer in CMDR should not commence with a START or REPEATED START condition.
Write this bit to one if the transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free
when the command is executed, a START condition is used, if the bus is busy, a REPEATED START is used.
Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode.
Command Register (CMDR)
STOP
30
22
14
6
-
CMDR
Read/Write
0x0C
0x00000000
START
29
21
13
5
-
REPSAME
SADR[6:0]
28
20
12
4
-
NBYTES
TENBIT
27
19
11
3
-
26
18
10
2
-
AT32UC3L016/32/64
SADR[9:7]
ACKLAST
25
17
9
1
PECEN
READ
24
16
8
0
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