AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 473

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.8.3
32099F–11/2010
Master Transmitter Mode
The interrupt system can be set up to give interrupt request on specific events or error condi-
tions, for example when the transfer is complete or if arbitration is lost.
The controller will refuse to start a new transfer while ANAK, DNAK or ARBLST is set in the
Status Register (SR). This is necessary to avoid a race when the software issues a continua-
tion of the current transfer at the same time as one of these errors happen. Also, if ANAK or
DNAK occur, a STOP condition is sent automatically. The programmer will have to restart the
transmission by clearing the errors bit in SR after resolving the cause for the NACK.
After a data or address NACK from the slave, a STOP will be transmitted automatically. Note
that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the
VALID bit can be cleared manually allowing any command in NCMDR to be copied into
CMDR.
When a data or address NACK is returned by the slave while the master is transmitting, it is
possible that new data has already been written to the THR register. This data will be trans-
ferred out as the first data byte of the next transfer. If this behavior is to be avoided, the safest
approach is to perform a software reset of the TWIM.
A START condition is transmitted and master transmitter mode is initiated when the bus is free
and CMDR has been written with START=1 and READ=0. START and SADR+W will then be
transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The
master polls the data line during this clock pulse and sets the Address Not Acknowledged bit
(ANAK) in the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with
no data bytes, ie START, SADR+W, STOP.
TWI transfers require the slave to acknowledge each received data byte. During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to
pull it down in order to generate the acknowledge. The master polls the data line during this
clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave
does not acknowledge the data byte. As with the other status bits, an interrupt can be gener-
ated if enabled in the Interrupt Enable Register (TWIM_IER).
1. Before any transfers can be performed, bus timings must be configured by program-
2. If a DMA controller is to be used for the transfers, it must be set up.
3. CMDR or NCMDR must be programmed with a value describing the transfer to be
1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY
2. Transmit this data byte
3. Decrement NBYTES
4. If (NBYTES==0) and STOP=1, transmit STOP condition
ming the Clock Waveform Generator Register (CWGR). If operating in SMBus mode,
the SMBus Timing Register (SMBTR) register must also be configured.
performed.
indicates the state of THR. Software or a DMA controller must write the data byte to
THR.
AT32UC3L016/32/64
473