AT32UC3L032-D3UR Atmel, AT32UC3L032-D3UR Datasheet - Page 332

• Manufacturer Part Number: AT32UC3L032-D3UR
• Description: MCU AVR32 32KB FLASH 48TLLGA
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3L032-D3UR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 1.62 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TLLGA
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: SPI, TWI, USART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 7
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: AT32UC3L-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 9 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.6.2.7
18.6.2.8
32099F–11/2010
Peripheral Events
CPU Local Bus
Figure 18-5. Interrupt Timing with Glitch Filter Enabled
The CPU Local Bus can be used for application where low latency read and write access to the
Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU
Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the
shared Peripheral Bus (PB).
To avoid data loss when using the CPU Local Bus, the CLK_GPIO must run at the same fre-
quency as the CLK_CPU. See
The CPU Local Bus is mapped to a different base address than the GPIO but the OVER and
ODER offsets are the same. See the CPU Local Bus Mapping section in the Memories chapter
for details.
Peripheral events allow direct peripheral to peripheral communication of specified events. See
the Peripheral Event System chapter for more information.
The GPIO can be programmed to output peripheral events whenever an interrupt condition is
detected. The peripheral events configuration depends on the interrupt configuration. An event
will be generated on the same condition as the interrupt (pin change, rising edge, or falling
edge). The interrupt configuration is controlled by the IMR register. Peripheral event on a pin is
enabled by writing a one to the corresponding bit in the Event Enable Register (EVER). The
Peripheral Event trigger mode is shared with the interrupt trigger and is configured by writing to
the IMR0 and IMR1 registers. Interrupt does not need to be enabled on a pin when peripheral
events are enabled. Peripheral Events are also affected by the Input Glitch Filter settings. See
Section 18.6.2.5
A peripheral event can be generated on each GPIO pin. Each port can then have up to 32
peripheral event generators. Groups of eight peripheral event generators in each port are ORed
together to form a peripheral event line, so that each port has four peripheral event lines con-
nected to the Peripheral Event System.
CLK_GPIO
Pin Level
IFR
for more information.
Section 18.5.2
for details.
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